Delta sigma circuit with pulse width modulated offset

A delta sigma analog-to-digital circuit, comprising:

• an integrator with an integrator input couplable to an analog signal and generating an integrated output;
• a comparator receiving the integrated output, and generating a comparison output;
• a controller receiving the comparison and generating a plurality of clocked control outputs and a converted output representing the analog signal;
• a balancing circuit receiving clocked control outputs and generating a balancing current to the integrator input wherein the balancing current changes polarity as a function of the controller outputs;
• and
• an offset circuit generating an offset current to the integrator input, the offset circuit including an electronic switch that is pulse width modulated by the controller to electrically offset the frequency of the converted output.

A delta sigma analog-to-digital circuit, comprising;

• a first-stage delta sigma modulator receiving an analog input signal and generating a first integrated signal;
• a second stage delta sigma modulator coupled to the first-stage delta sigma modulator and receiving the first integrated signal and generating a second integrated signal;
• a comparator comparing the second integrated signal to a reference level and generating a latched output as a function of the comparison;
• a controller controlled by the latched output, the controller generating a plurality of control signals to the first stage delta sigma modulator and a converted digital output signal;
• and
• the first stage modulator further including a pulse width modulated offset circuit that offsets the operation of the circuit.

A delta sigma method of converting an analog signal to a digital signal, comprising;

• integrating the analog signal and a balancing current in an integrator;
• alternating the balancing current between a first polarity and a second polarity;
• comparing the integrator output to a reference;
• controlling the alternating of the balancing current at clocked time intervals as a function of the comparing;
• pulse width modulating an offset current to control its amplitude;
• and
• integrating an offset current in the integrator to offset the clocking of the alternating away from an interfering frequency.

A computer-readable medium having stored thereon a plurality of sequences of instructions, the plurality of sequences of instructions including sequences that, when executed by a controller in a delta sigma analog to digital converter, cause the delta sigma analog to digital converter to perform a sequence, comprising:

• integrating an analog signal and a balancing current in an integrator;
• alternating the balancing current between a first polarity and a second polarity;
• comparing the integrator output to a reference;
• controlling the alternating of the balancing current at clocked time intervals as a function of the comparing;
• pulse width modulating the offset current to control its amplitude;
• and
• integrating an offset current in the integrator to offset the clocking of the alternating away from an interfering frequency.

A delta sigma analog-to-digital circuit, comprising;

• a first-stage delta sigma modulator receiving an analog input signal and generating a first integrated signal;
• a second stage delta sigma modulator coupled to the first-stage delta sigma modulator and receiving the first integrated signal and generating a second integrated signal;
• a comparator comparing the second integrated signal to a reference level and generating a latched output as a function of the comparison;
• a controller controlled by the latched output, the controller generating a plurality of control signals to the first stage delta sigma modulator and a converted digital output signal;
• and
• offset circuit means coupled to the first stage delta sigma modulator for pulse-width-modulating an offset current in the first stage delta sigma modulator.