Offset-compensated amplifier input stage and method

An amplifier circuit, comprising:

• (a) a current source;
• (b) first and second cascode transistors each having a first electrode coupled to the current source and a control electrode, a first adjustment signal being applied to the control electrode of at least one of the first and second cascode transistors;
• (c) first and second input transistors each having a first electrode coupled to a second electrode of the first cascode transistor;
• (d) third and fourth input transistors each having a first electrode coupled to a second electrode of the second cascode transistor, the W/L ratios of the first and second input transistors being related by a predetermined ratio, the W/L ratios of the fourth and third input transistors being related by the predetermined ratio a control electrode of each of the first and third input transistors being coupled to a first input terminal, a control electrode of each of the second and fourth input transistors being coupled to a second input terminal;
• (e) a second electrode of each of the first and third input transistors being coupled by a first output conductor to a first load device;
• and
• (f) a second electrode of each of the second and fourth input transistors being coupled by a second output conductor to a second load device.

An offset-compensated amplifier, comprising:

• (a) an input stage including
• i. a current source, and first and second compensation transistors each having a first electrode coupled to the current source,
• ii. first and second input transistors each having a first electrode coupled to a second electrode of the first compensation transistor, and third and fourth input transistors each having a first electrode coupled to a second electrode of the second compensation transistor, the W/L ratios of the first and second input transistors being related by a predetermined ratio, the W/L ratios of the fourth and third input transistors being related by the predetermined ratio, a second electrode of each of the first and third input transistors being coupled by a first output conductor to a first load device, and a second electrode of each of the second and fourth input transistors being coupled by a second output conductor to a second load device, a control electrode of each of the first and third input transistors being coupled to a first input terminal, a control electrode of each of the second and fourth input transistors being coupled to a second input terminal;
• and
• (b) auto-zeroing circuitry coupled to the first and second input terminals and the first and second output conductors, including switching circuitry operative to short-circuit the first and second input terminals together to cause the input stage to produce an offset signal between the first and second output conductors, switched capacitor circuitry operative to store a signal representative of the offset signal, and compensation circuitry operative to apply compensation signals to the control electrodes of the first and second compensation transistors in response to the stored offset signal.

An offset-compensated amplifier, comprising:

• (a) a current source;
• (b) first and second compensation transistors each having a first electrode coupled to the second current source;
• (c) first and second input transistors each having a first electrode coupled to a second electrode of the first compensation transistor, and third and fourth input transistors each having a first electrode coupled to a second electrode of the second compensation transistor, the W/L ratios of the first and second input transistors being related by a predetermined ratio, the W/L ratios of the fourth and third input transistors being related by the predetermined ratio;
• (d) a second electrode of each of the first and third input transistors being coupled by a first output conductor to a first load device, and a second electrode of each of the second and fourth input transistors being coupled by a second output conductor to a second load device;
• (e) a control electrode of each of the first and third transistors being coupled to a first input terminal, a control electrode of each of the second and fourth transistors being coupled to a second input terminal;
• (f) first and second auto-zeroing switches operative to short-circuit the first and second input terminals together;
• (g) third and fourth auto-zeroing switches operative to store voltages on the first and second output conductors on a first capacitor and a second capacitor, respectively;
• and
• (h) circuitry receiving the voltages stored on the first and second capacitors and applying corresponding compensation voltages to control electrodes of the first and second compensation transistors, respectively.

A method of compensating the input offset voltage of an amplifier, comprising:

• (a) splitting a tail current into a first current flowing through a first MOSFET and a second current flowing through a second MOSFET;
• (b) splitting the first current into a third current flowing through a first input MOSFET having its gate connected to a first input terminal and a fourth current flowing thorough a second input MOSFET having its gate connected to a second input terminal, and splitting the second current into a fifth current flowing through a third input MOSFET having its gate connected to the first input terminal and a sixth current flowing through a fourth input MOSFET having its gate connected to the second input terminal, the W/L ratios of the first and second input MOSFETs being related by a predetermined ratio, the W/L ratios of the fourth and third input MOSFETs being related by the predetermined ratio;
• (c) directing the third and fifth currents to flow through a first output conductor into a first load device and directing the fourth and sixth currents to flow through a second output conductor into a second load device;
• (d) short-circuiting the first and second input terminals to a predetermined voltage to cause a gained-up offset voltage to be developed between the first and second output conductors;
• (e) storing a voltage representative of the gained-up offset voltage in a sample-and-hold circuit;
• and
• (f) producing an adjustment voltage representative of the sampled and held gained-up offset voltage and applying the adjustment voltage between the gates of the first and second MOSFETs to cause the amplifier to operate to reduce the gained-up offset voltage.

An adjustable offset amplifier circuit, comprising:

• (a) a current source;
• (b) first and second compensation transistors each having a first electrode coupled to the second current source;
• (c) first and second input transistors each having a first electrode coupled to a second electrode of the first compensation transistor, and third and fourth input transistors each having a first electrode coupled to a second electrode of the second compensation transistor, the W/L ratios of the first and second input transistors being related by a predetermined ratio, the W/L ratios of the fourth and third input transistors being related by the predetermined ratio;
• (d) a second electrode of each of the first and third input transistors being coupled by a first output conductor to a first load device, and a second electrode of each of the second and fourth input transistors being coupled by a second output conductor to a second load device;
• (e) a control electrode of each of the first and third transistors being coupled to a first input terminal, a control electrode of each of the second and fourth transistors being coupled to a second input terminal;
• and
• (f) offset control circuitry producing at least one control voltage in response to an offset adjustment signal and applying the control voltage to a control electrode of one of the first and second compensation transistors, respectively.