Dual damascene processing for semiconductor chip interconnects

A method for forming an interconnect structure on the upper surface of a substrate having conductive regions comprising the steps of:

• forming over said substrate a first dielectric layer having a thickness corresponding to the thickness of an interconnect via,
• forming over said first dielectric layer a second dielectric layer having a thickness corresponding to the thickness of an interconnect wiring layer,
• forming a first hard mask layer over said second layer,
• forming a layer of resist over said first hard mask layer,
• patterning said layer of resist with a via pattern,
• patterning said first hard mask layer using said via-patterned layer of resist as a mask,
• transferring said via pattern into said second dielectric layer to form via cavities corresponding to said via pattern, while concurrently removing said via-patterned layer of resist,
• forming a third layer of liner material over said first hard mask layer and on the sidewalls and bottom of said via cavities,
• forming a layer of resist over said third layer,
• patterning said layer of resist with a wiring pattern,
• patterning said third layer and said first hard mask layer using said wiring-patterned layer of resist as a mask,
• transferring, at least partially concurrently, said wiring pattern into said second dielectric layer to form wiring cavities corresponding to said wiring pattern, and said via pattern into said first dielectric layer to form via cavities corresponding to said via pattern, while concurrently removing said wiring-patterned layer of resist,
• filling said cavities with conductive material to make electrical contact to said conductive regions and to form said vias and said wiring pattern.

A method for forming an interconnect structure on the upper surface of a substrate having conductive regions comprising the steps of:

• forming over said substrate a first dielectric layer having a thickness corresponding to the thickness of an interconnect via,
• forming over said first dielectric layer a second dielectric layer having a thickness corresponding to the thickness of an interconnect wiring layer,
• forming a first hard mask layer over said second layer,
• forming a second hard mask layer over said first hard mask layer, said second hard mask layer preferably formed of a material different from said first hard mask to permit selective etching of said second hard mask layer with respect to said first hard mask layer,
• forming a first layer of resist over said second hard mask layer,
• patterning said first layer of resist with a wiring pattern,
• patterning said second hard mask layer using said wiring-patterned first layer of resist as a mask,
• removing said wiring-patterned first layer of resist,
• forming a second layer of resist over said first and second hard mask layer,
• patterning said second layer of resist with a via pattern,
• patterning said first hard mask layer using said via-patterned second layer of resist as a mask,
• transferring said via pattern in said patterned first hard mask layer into said second dielectric layer, while concurrently removing said via-patterned second layer of resist, and
• patterning said via-patterned first hard mask layer using said wiring-patterned second hard mask layer as a mask,
• transferring, at least partially concurrently, said via pattern into said first dielectric layer to form via cavities corresponding to said via pattern, and said wiring pattern into said second dielectric layer to form wiring cavities corresponding to said wiring pattern, and
• filling said cavities with conductive material to make electrical contact with said conductive regions and to form said vias and said wiring pattern.

A method for forming an interconnect structure on the upper surface of a substrate having conductive regions comprising the steps of:

• forming over said substrate a first dielectric layer having a thickness corresponding to the thickness of an interconnect via,
• forming over said first dielectric layer a second dielectric layer having a thickness corresponding to the thickness of an interconnect wiring layer,
• forming a first hard mask layer over said second layer,
• forming a second hard mask layer over said first hard mask layer, said second hard mask layer preferably formed of a material different from said first hard mask to permit selective etching of said second hard mask layer with respect to said first hard mask layer,
• forming a third hard mask layer over said second hard mask layer, said third hard mask layer formed of a material different from said second hard mask to permit selective etching of said third hard mask layer with respect to said second hard mask layer,
• forming a first layer of resist over said third hard mask layer,
• patterning said first layer of resist with a wiring pattern,
• patterning said third hard mask layer using said wiring-patterned first layer of resist as a mask,
• removing said patterned first layer of resist,
• forming a second layer of resist over said second and third hard mask layer,
• patterning said second layer of resist with a via pattern,
• patterning said second hard mask layer using said via-patterned second layer of resist as a mask,
• patterning said first hard mask layer using said via-patterned second hard mask layer as a mask,
• transferring said via pattern in said patterned first hard mask layer into said second dielectric layer while concurrently removing any residuals of said patterned second layer of resist,
• patterning said second hard mask layer using said wiring-patterned third hard mask layer as a mask,
• patterning said first hard mask layer using said wiring-patterned second hard mask layer as a mask,
• transferring, at least partially concurrently, said via pattern into said first dielectric layer to form via cavities corresponding to said via pattern, and said wiring pattern into said second layer to form wiring cavities corresponding to said wiring pattern, and
• filling said cavities with conductive material to make electrical contact with said conductive regions and to form said vias and said wiring pattern.

A method for forming an interconnect structure on the upper surface of a substrate having conductive regions comprising the steps of:

• forming over said substrate a first dielectric layer having a thickness corresponding to the thickness of an interconnect via,
• forming over said first dielectric layer a second dielectric layer having a thickness corresponding to the thickness of an interconnect wiring layer
• forming a first hard mask layer over said second dielectric layer,
• forming a second hard mask layer over said first hard mask layer, said second hard mask layer preferably formed of a material different from said first hard mask to permit selective etching of said second hard mask layer with respect to said first hard mask layer,
• forming a first layer of resist over said second hard mask layer,
• patterning said first layer of resist with a via pattern,
• patterning said second hard mask layer using said via-patterned first layer of resist as a mask,
• removing said first layer of resist,
• forming a second layer of resist over said first and second hard mask layer,
• patterning said second layer of resist with a wiring pattern,
• patterning said second hard mask layer using said wiring-patterned second layer of resist as a mask while patterning said first hard mask layer using said via-patterned second hard mask layer as a mask,
• transferring said via pattern in said patterned first hard mask layer into said second dielectric layer, while concurrently removing any residuals of said patterned second layer of resist,
• transferring, at least partially concurrently, said via pattern into said first dielectric layer to form via cavities corresponding to said via pattern, and said wiring pattern into said second layer to form wiring cavities corresponding to said wiring pattern,
• filling said cavities with conductive material to make electrical contact with said conductive regions and to form said vias and said wiring pattern.