Programmable interconnect matrix architecture for complex programmable logic device

Abstract

Routing an input signal to an output of a programmable interconnect matrix is accomplished via multi-level routing architecture. The routing may include selecting the input signal from a number of input signals at a first level of the routing architecture to provide an intermediate signal. The intermediate signal may then be selected at a second level of the routing architecture to provide the output signal. Selecting the input signal and/or the intermediate signal may be accomplished by programming one or more mutliplexers. In a further embodiment, the method includes dividing a plurality of input signals into segments, each segment including a number of the plurality input signals. From the segments, at least one of the input signals may be selected to produce the intermediate signal. Further still, a method of interconnecting signals by coupling an input of a connection circuit of a programmable logic device to an output thereof through a multi-level routing architecture within the connection circuit is provided. The coupling may be accomplished by first coupling the input to a first intermediate signal path at a first level of the multi-level routing architecture and then coupling the intermediate signal path to the output at a second level of the multi-level routing architecture. In each case, the coupling may be accomplished by appropriate selection using one or more multiplexers at the various levels of the multi-level routing architecture.

Dependencies are inferred from the claim text.