Method for planarized interconnect vias using electroless plating and CMP
AssigneeChartered Semiconductor Manufacturing Ltd.
InventorsLap Chan, Hou Tee Ng
Life of this patent
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Abstract
An improved and new method for fabricating conducting vias between successive layers of conductive interconnection patterns in a semiconductor integrated circuit has been developed. The method utilizes a first CMP step to form a barrier lined contact hole, deposition of copper by electroless plating into the barrier lined contact hole, and a second CMP step to remove overgrowth of copper, thus producing coplanarity between the copper surface and the surrounding insulator surface.
Claims34
A method of fabrication of integrated circuit interconnection vias on a semiconductor substrate having an insulating layer, said insulating layer having contact openings etched therein, comprising the steps of:
- providing said semiconductor substrate having an insulating layer containing contact openings etched therein;
- forming a barrier layer, comprising TiN, WN or TaN onto the surface of the insulating layer and into the contact openings, forming said barrier layer onto the sidewalls and bottom of said contact openings;
- using a first CMP (Chemical Mechanical Polishing) to remove said barrier layer from the surface of said insulating layer, leaving contact openings lined with said barrier layer;
- cleaning said semiconductor substrate;
- forming an activation layer comprising Pd or Pt onto the barrier layer lining said contact openings;
- depositing copper by electroless plating onto said activation layer as formed onto said barrier layer lining said contact openings;
- continuing deposition of copper by electroless plating to fill said contact openings and result in an overgrowth of copper above the surface of the insulating layer;
- and
- using a second CMP (Chemical Mechanical Polishing) to remove said overgrowth of copper, thereby producing coplanar surfaces of copper and insulating layer materials.
A method of fabricating a MOSFET device on a semiconductor substrate, wherein contact to the active device element comprises the steps of:
- providing said active device element in said semiconductor substrate;
- depositing an interlevel dielectric layer on said semiconductor substrate, that includes said active device element;
- providing a contact opening, etched through said interlevel dielectric layer, to said active device element;
- forming a barrier layer, comprising TiN, WN or TaN onto the surface of the interlevel dielectric layer and into the contact opening, forming said barrier layer onto the sidewalls and bottom of said contact opening;
- using a first CMP (Chemical Mechanical Polishing) to remove said barrier layer from the surface of said interlevel dielectric layer, leaving said contact opening lined with said barrier layer;
- cleaning said semiconductor substrate;
- forming an activation layer comprising Pd or Pt onto the barrier layer lining said contact opening;
- depositing copper by electroless plating onto said activation layer as formed onto said barrier layer lining said contact opening;
- continuing deposition of copper by electroless plating to fill said contact opening and result in an overgrowth of copper above the surface of the interlevel dielectric layer;
- and
- using a second CMP (Chemical Mechanical Polishing) to remove said overgrowth of copper, thereby producing coplanar surfaces of copper and interlevel dielectric layer materials.
A method of fabrication of an interconnection layer in an integrated circuit comprising:
- depositing an insulating layer over a metallization pattern;
- providing contact openings, etched through said insulating layer and exposing elements of said metallization pattern;
- forming a barrier layer, comprising TiN, WN or TaN onto the surface of said insulating layer and into said contact openings, forming said barrier layer onto the sidewalls and bottom of said contact openings;
- using a first CMP (Chemical Mechanical Polishing) to remove said barrier layer from the surface of said insulating layer, leaving contact openings lined with said barrier layer;
- cleaning said semiconductor substrate;
- forming an activation layer comprising Pd or Pt onto the barrier layer lining said contact openings;
- depositing copper by electroless plating onto said activation layer as formed onto said barrier layer lining said contact openings;
- continuing deposition of copper by electroless plating to fill said contact openings and result in an overgrowth of copper above the surface of the insulating layer;
- and
- using a second CMP (Chemical Mechanical Polishing) to remove said overgrowth of copper, thereby producing coplanar surfaces of copper and insulating layer materials.
Dependencies are inferred from the claim text.