Reducing power consumption in computer memory

A computer system comprising:

• an input device;
• a memory device that stores data;
• a processor capable of receiving an input signal from said input device, said processor being adapted to access said memory device;
• and
• a refresh logic that provides a periodic refresh signal to refresh said memory device, wherein said refresh logic is capable of selectively varying the rate of the refresh signal as a function of time;
• wherein said refresh logic provides the refresh signal at a first refresh rate for a first predetermined period of time and provides the refresh signal at a second refresh rate after the first predetermined time period elapses;
• and
• wherein said refresh logic comprises a counter which generates a select signal when the first predetermined time period has expired, the select signal causing said refresh logic to provide the refresh signal at the second refresh rate.

A computer system comprising:

• an input device;
• a memory device that stores data;
• processor capable of receiving an input signal from said input device, said processor being adapted to access said memory device;
• and
• a refresh logic that provides a periodic refresh signal to refresh said memory device, wherein said refresh logic is capable of selectively varying the rate of the refresh signal as a function of time;
• wherein said refresh logic provides the refresh signal at a first refresh rate for a first predetermined period of time and provides the refresh signal at a second refresh rate after the first predetermined time period elapses;
• and
• wherein said refresh logic provides the refresh signal at the second refresh rate for a second predetermined period of time and provides the refresh signal at a third refresh rate after the second predetermined time period elapses.

A computer system comprising:

• an input device;
• a memory device that stores data;
• a refresh logic that provides a periodic refresh signal to refresh said memory device, wherein said refresh logic is capable of selectively varying the rate of the refresh signal as a function of time;
• a processor capable of receiving an input signal from said input device, said processor being adapted to access said memory device, wherein said processor asserts a select signal to said refresh logic to cause said refresh logic to vary the refresh rate;
• and
• a counter which asserts an interrupt signal to said processor after a predetermined period of time, said interrupt signal causing said processor to assert said select signal.

A memory device comprising:

• a refresh logic unit that provides an internal refresh signal having a variable refresh frequency;
• and
• a switch through which said memory device receives a select signal and an external refresh signal;
• wherein said memory device uses the internal refresh signal to refresh memory if the select signal is asserted and uses the external refresh signal to refresh memory if the select signal is deasserted.

In a computer system having a processor receiving input signals from an input device and a memory device that stores data, a method of reducing power consumption in the computer system comprising:

• operating the computer system in a low power mode of operation, and while the computer system is in a low power mode of operation;
• providing a periodic refresh signal to the memory device;
• and
• slowing the rate of the periodic refresh signal to slow the refresh rates of the memory device as the memory device becomes able to retain data with a slower refresh rate.

A computer system, comprising:

• an input device;
• a memory device that stores data;
• a processor that receives an input signal from an input device and that accesses said memory device;
• and
• a refresh logic adapted to provide a refresh signal to refresh said memory device, wherein the refresh logic is further adapted to vary the rate of the refresh signal based on a selected parameter after the computer system is placed in a suspend mode.