Semiconductor memory device with several access enabled using single port memory cell

A semiconductor memory device comprising:

• a plurality of word lines;
• a plurality of bit lines;
• a plurality of memory cells arranged in a matrix, wherein each of said plurality of memory cells is connected to one of said plurality of word lines and is connected to one of said plurality of bit lines such that a plurality of columns are formed from said plurality of memory cells;
• a word line selecting section for selecting one of said plurality of word lines based on a first address;
• a first column selector connected to said plurality of columns, for selecting one of said plurality of columns as a first column based on said first address;
• a second column selector connected to said plurality of columns, for selecting another one of said plurality of columns as a second column based on a second address, an address data of a predetermined portion of said first address being not equal to an address data of said second address;
• and
• an input/output section which includes a first sense amplifier connected to said first column selector and a first buffer connected to said second column selector,
• wherein a first read operation is performed to a first memory cell connected to said selected word line and said first column through said first sense amplifier and said first column selector and a first write operation is performed to a second memory cell connected to said selected word line and said second column through said first buffer and said second column selector.