Nonvolatile semiconductor memory device with soft-programming to adjust erased state of memory cells

A nonvolatile semiconductor memory device comprising:

• a memory cell array comprising memory cells arranged in rows and columns, each having a control gate;
• a programming circuit for programming data into any selected one of said memory cells by applying a program voltage to the control gate of the selected memory cell;
• an erasing circuit for erasing data from said memory cells by applying an erase voltage opposite in polarity to the program voltage;
• a soft-programming circuit for applying a soft-program voltage to said memory cells after said erasing circuit has erased data from said memory cells, thereby setting said memory cells into a desirable erased state;
• a verification read circuit for determining whether said memory cells have been set into the desirable erased state after said soft-programming circuit has soft-programmed said memory cells;
• and
• an erased-state determining circuit for causing said soft-programming circuit to terminate a soft-program operation upon determining from an output of said verification read circuit that at least two of said memory cells have a threshold voltage which has reached a predetermined value.

A nonvolatile semiconductor memory device comprising:

• at least three memory cells, each having a control gate;
• a programming circuit configured to program data into any selected one of said memory cells by applying a program voltage to the control gate of the selected memory cell;
• an erasing circuit configured to erase data from all of said memory cells by simultaneously applying an erase voltage opposite in polarity to the program voltage to all of said memory cells, thereby setting all of said memory cells into an erased state;
• a soft-programming circuit configured to simultaneously apply a soft-program voltage having the same polarity with the program voltage to the control gates of all said memory cells in order to adjust the erased state of said memory cells;
• a verification read circuit configured to determine whether threshold voltages of at least two of said memory cells have entered a given range and configured to output a termination signal if it is determined that the threshold voltages of at least two of said memory cells have entered the given range;
• and
• an erased-state determining circuit configured to cause said soft-programming circuit to terminate the applying of the soft-program voltage in response to the termination signal.