Liquid level sensor
AssigneeAmerican Standard Inc.
InventorsRonald W. Okoren, Ali S. Ameen, Matthew A. Shepeck
Life of this patent
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Abstract
A sensor system. The system comprises a binary sensor issuing a signal representative of a first or second condition; sampling circuitry, operatively connected to the binary sensor, for monitoring the number of transitions between the first and second conditions during a sampling period; integration circuitry for accumulating the sampled number of transitions over time; and signal generation circuitry for issuing an analog signal representative of the accumulated transitions.
Claims12
A sensor system comprising:
- a binary sensor having an optical sensing mechanism issuing a signal representative of a first or second condition;
- sampling circuitry, operatively connected to the binary sensor, for monitoring the number of transitions between the first and second conditions during a sampling period;
- integration circuitry for accumulating the sampled number of transitions over time;
- and
- signal generation circuitry for issuing an analog signal representative of the accumulated transitions.
A sensor system comprising:
- a binary sensor issuing a signal representative of a first or second condition;
- sampling circuitry, operatively connected to the binary sensor, for monitoring the number of transitions between the first and second conditions during a sampling period;
- integration circuitry for accumulating the sampled number of transitions over time;
- and
- signal generation circuitry for issuing an analog signal representative of the accumulated transitions;
- wherein the integration circuitry includes an integration control which selects a first level of accumulated transitions above which integration is enabled.
A method of using a digital sensor as an analog sensor comprising the steps of:
- measuring a binary state with a digital sensor;
- constantly transmitting a first binary signal indicative of a first inactive state or a second binary signal indicative of a second active state;
- sampling the transmitted signal at a first sampling rate to determine a bit count;
- integrating the product of the bit count over time;
- and
- issuing either an analog signal reflective of the integrated bit count accumulation or a digital signal reflective of an inactive or active state.
A method of using a digital sensor as an analog sensor comprising the steps of:
- measuring a binary state with a digital sensor;
- constantly transmitting a binary signal indicative of either a first or a second binary state;
- sampling the transmitted signal at a first sampling rate to determine a bit count;
- integrating the product of the bit count over time;
- and
- issuing an analog signal reflected of the integrated bit count accumulation;
- wherein the integrating step is implemented only if the bit count is above a first predetermined level and the accumulated integral is cleared if the bit count falls below a second predetermined level less than the first predetermined level.
Circuitry for using a digital sensor as an analog sensor comprising:
- a digital sensor having an optical sensor mechanism issuing a binary signal having a first or a second state;
- sampling circuitry for receiving the binary signal, for sampling the state of the binary signal at a moment in time, and for converting the sampled signal to a signal representative of a bit count;
- integrator circuitry to integrate the bit count over time;
- and
- circuitry to transmit an analog signal representative of the accumulated integral.
Circuitry for using a digital sensor as an analog sensor comprising:
- a digital sensor issuing a binary signal having a first or second state;
- sampling circuitry for receiving the binary signal, for sampling the state of the binary signal at a moment in time, and for converting the sampled signal to a signal representative of a bit count;
- integrator circuitry to integrate the bit count over time;
- and
- circuitry to transmit an analog signal representative of the accumulated integral;
- further including a filter and voltage divider in the sampling circuitry, and including an integrator controller in the integration circuitry to implement integration above a first bit count level and to clear the accumulated integral below a second bit count level.
Dependencies are inferred from the claim text.