Programmable address decoder for field programmable memory array
AssigneeInternational Business Machines Corporation
InventorsScott Whitney Gould, Joseph Andrew Iadanza, Frank Ray Keyser, III, Terrance John Zittritsch
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Abstract
A field programmable memory array having a plurality of sub-arrays is provided. Programmable address decoders, programmable hierarchical bit line arrangements, programmable I/O arrangements, among other features, are provided to enable programming of portions of the array into selected modes. The modes may include wide memory, deep memory, FIFO, LIFO, among others. An embodiment of the invention is disclosed wherein the field programmable memory array is integrated with the programmable resources of a field programmable gate array.
Claims21
A programmable address decoder comprising:
- M word lines;
- a plurality of address lines for propagating address data;
- a programmable inverter disposed in series with a given address line of said plurality of address lines, said programmable inverter selectively inverting a signal propagating along said given address line in accordance with an address polarity select signal;
- and
- a decoder circuit selectively driving a given word line of said M word lines as selected in accordance with address data of said plurality of address lines as processed per said programmable inverter.
A programmable address decoder comprising:
- M word lines;
- a plurality of address lines for propagating address data;
- a decoder circuit selectively driving a given word line of said M word lines as selected in accordance with address data of said plurality of address lines;
- and
- a selective coupler having a plurality of inputs coupled to an associated set of lines of an address bus, and an output coupled to an address line of said plurality of address lines, said selective coupler selectively coupling its output to one of its plurality of inputs in accordance with associated configuration data.
A programmable address decoder comprising:
- M word lines;
- a plurality of address inputs for receiving address data;
- an enable input for receiving an enable signal;
- logic means for selectively driving one word line of said M word lines when its associated address data is received at said plurality of address inputs and when enabled per said enable signal;
- and
- non-clock programmable means for providing said enable signal in accordance with an enable select signal.
A programmable address decoder according to claimn 9, wherein said high order address decoder circuit comprises:
- an AND gate having an output coupled for driving said high address enable input, and a plurality of inputs for receiving said high order addressing data.
A programmable address decoder comprising:
- M word lines;
- a plurality of address inputs for receiving address data;
- an enable input for receiving an enable signal;
- logic means for selectively driving one word line of said M word lines when its associated address data is received at said plurality of address inputs and when enabled per said enable signal;
- and
- programmable means for providing said enable signal in accordance with an enable select signal, wherein said programmable means comprises:
- an enable multiplexer having a first input coupled for receiving an enable source signal and a second input coupled for receiving a fixed signal, wherein said enable multiplexer provides said enable signal per one of the enable source signal or the fixed signal as selected in accordance with said enable select signal.
A memory array having:
- a plurality of memory cells arranged in rows and columns, said rows of memory cells being selectable per respective word lines for loading data therein, said plurality of memory cells sharing a common reset signal;
- and
- a programmable address decoder having M word line outputs coupled to the respective word lines of said plurality of rows of memory cells, a plurality of inputs for receiving address data for addressing select word line outputs in accordance with said address data, and a reset disable input for receiving said common reset signal, said programmable address decoder disabling said M word line outputs in accordance with said common reset signal.
Dependencies are inferred from the claim text.