Digital demodulators for phase modulated and amplitude-phase modulated signals

A phase demodulator comprising:

• sampling means for periodically sampling logical values of a phase-modulated signal waveform-shaped into a binary pulse signal to thereby generate a serial code train;
• serial/parallel converting means for converting the serial code train into a parallel code train of a predetermined bit length for each predetermined interval;
• code analyzing means for logically detecting phase difference information, based on a logical pattern displacement on a time sequence of the parallel code train;
• data determining means for generating demodulated data, based on the output of said code analyzing means;
• said sampling means and said converting means including a plurality of shift registers to which the phase-modulated signal is inputted in common and which respectively output the parallel code train;
• and
• a multi-phase clock generator for distributing clock signals identical in period to each other and different in phase from each other to said respective shift registers.

A phase demodulator comprising:

• sampling means for periodically sampling logical values of a phase-modulated signal waveform-shaped into a binary pulse signal to thereby generate a serial code train;
• serial/parallel converting means for converting the serial code train into a parallel code train of a predetermined bit length for each predetermined interval;
• code analyzing means for logically detecting phase difference information, based on a logical pattern displacement on a time sequence of the parallel code train;
• data determining means for generating demodulated data, based on the output of said code analyzing means;
• said sampling means including a frequency divider for by-1/2 dividing the phase-modulated signal to produce a divided phase modulated signal;
• and
• wherein said sampling means and converting means perform a process for sampling logical values of a phase-modulated signal by-1/2 divided by said frequency divider and performing serial/parallel conversion on them.

An amplitude phase demodulator comprising:

• a phase detection unit for detecting a phase component of a received amplitude phase-modulated signal;
• an amplitude detection unit for detecting an amplitude component of the received amplitude phase-modulated signal;
• a data determinator for determining received data from the output of said phase detection unit and the output of said amplitude detection unit;
• a symbol clock reproducer for reproducing a symbol clock synchronized with the received signal from the output of said phase detection unit;
• said amplitude detection unit waveform-shaping the received signal into a binary pulse signal using a nonlinear amplifier having one or two or more different threshold values and determining the presence or absence of the pulse signal, thereby detecting amplitude information;
• and
• said amplitude detection unit comprising a received strength determinator for determining a received strength from a plurality of pieces of amplitude information each having been determined as to the presence or absence of a pulse signal, which are produced from outputs of nonlinear amplifiers each having one or more different threshold values, and a signal selector for selecting the optimum amplitude information from the plurality of pieces of amplitude information, based on the result of determination by said received strength determinator.

An amplitude phase demodulator comprising:

• a phase detection unit for detecting a phase component of a received amplitude phase-modulated signal;
• an amplitude detection unit for detecting an amplitude component of the received amplitude phase-modulated signal;
• a data determinator for determining received data from the output of said phase detection unit and the output of said amplitude detection unit;
• a symbol clock reproducer for reproducing a symbol clock synchronized with the received signal from the output of said phase detection unit;
• said amplitude detection unit waveform-shaping the received signal into a binary pulse signal using a nonlinear amplifier having one or two or more different threshold values and determining the presence or absence of the pulse signal, thereby detecting amplitude information;
• and
• a set/reset type flip-flop reset for each symbol reproduced by said symbol clock reproducer that makes a decision as to the presence or absence of the pulse signal to thereby detect amplitude information.