QMOS digital logic circuits
AssigneeBoard of Regents, The University of Texas System
InventorsPoras T. Balsara, Kamal J. Koshy
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Abstract
Circuit designs of basic digital logic gates are disclosed using Resonant Tunneling Diodes (RTDs) and MOSFETs, which reduces the number of devices used for logic design, while exploiting the high speed negative differential resistance (NDR) characteristics of RTDs. Such logic circuits include NAND, NOR, AND, and OR gates and Minority/Majority circuits, which are used in full adder circuits. By implementing RTDs along with conventional MOSFETs, the use of series connected MOSFETs, which results in low output rise and fall times, especially for a large number of inputs, can be avoided. Furthermore, the RTD logic design styles do not require the use of resistors or any elaborate clocking or resetting scheme.
Claims24
A digital logic circuit, comprising:
- a pull-down circuit having at least two n-type transistors connected in parallel with a resonant tunneling diode, first and second inputs being applied to the gates of first and second ones of said n-type transistors, respectively;
- and
- a pull-up circuit having at least one p-type transistor operatively connected in series with said pull-down circuit,
- whereby propagation delay through said digital logic circuit is reduced.
A digital logic circuit, comprising:
- a pull-up circuit having at least three n-type transistors connected in parallel, first and second inputs being applied to the gates of first and second ones of said n-type transistors, respectively;
- and
- a pull-down circuit having a resonant tunneling diode operatively connected in series with said pull-up circuit,
- whereby propagation delay through said digital logic circuit is reduced.
A full adder circuit, comprising:
- a carry out circuit having first, second and third n-type transistors connected in parallel with a first resonant tunneling diode, first, second and third inputs being applied to the gates of said first, second and third n-type transistors, respectively, said first, second and third n-type transistors and said first resonant tunneling diode being connected in series with a first p-type transistor;
- and
- a sum circuit having fourth, fifth and sixth n-type transistors connected in parallel with a second resonant tunneling diode, said first, second and third inputs being applied to said fourth, fifth and sixth n-type transistors, respectively, said fourth, fifth and sixth n-type transistors being connected in series with a second p-type transistor, said second p-type transistor being connected in parallel with a third p-type transistor, the output of said carry out circuit being applied to the gate of said third p-type transistor through an inverter,
- whereby propagation delay through said carry out circuit is reduced.
Dependencies are inferred from the claim text.