US 6,130,458 AGranted

Power IC having SOI structure

AssigneeKabushiki Kaisha Toshiba

InventorsYosuke Takagi, Koichi Endo

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Abstract

The present invention relates in general to power ICs, etc. having the SOI structure, and more specifically to the structure in which an SOI substrate comprises a base substrate, an SOI oxide film formed on the base substrate, and active layers formed on the SOI oxide film, and also integrates on itself power devices and the corresponding control elements monolithically. Between this base substrate and this SOI oxide film is formed heavily-doped semiconductor regions having a conductivity type opposite to that of this base substrate. Hence, the junction capacitance between the base substrate and the heavily-doped semiconductor regions decreases an actual capacitance between the base substrate and the active layer so that to inhibit or prevent inversion layers from being formed at the bottom of the active layers.

Claims16

Dependent claims

A power IC having high-side and low-side circuits connected in series, a connection point between the high-side and low-side circuits oscillating between predetermined voltage levels, the high-side circuit having a high-side power element and a high-side control circuit for providing a high-side control signal to the high-side power element, the low-side circuit having a low-side power element and a low-side control circuit for providing a low-side control signal independent from the high-side control signal to the low-side power element, higher voltage being applied to the high-side power element than that applied to the low-side power element the power IC comprising:

a first semiconductor region which acts as a base substrate;
an insulator film formed on the first semiconductor region;
a second semiconductor region formed on top of the insulator film so as to form a SOI structure with said first semiconductor region and insulator flim, the SOI structure serving as a first capacitor;
element isolation regions devising said second semiconductor region into dielectrically isolated first, second, third, and fourth active layers, so as to form said high-side power element, high-side control circuit, low-side power element, and low-side control circuit therein, respectively;
a third semiconductor region having a conductivity type opposite to that of the first semiconductor region, selectively disposed in vicinity of a boundary between the first semiconductor region and the insulator film, and disposed at a top surfaces of the first semiconductor region, the third semiconductor region having a specific impurity concentration and diffusion depth so as to develop a large width depletion layer between said third and first semiconductor regions such that a second capacitor being connected between said third and first semiconductor regions, the second capacitor being connected to said first capacitor so that the second capacitor suppresses generations of inversion layers, which tend to be formed at bottoms of said first and second active layers at floating potentials, the bottoms being contacted with the insulator film, said first capacitor being connected between said third and second semiconductor regions;
a groove which starts at a top surface of said first active layer, penetrates through said first active layer and said insulator film, and reaches said third semiconductor region;
a high-conductivity region formed inside the groove;
a fourth semiconductor region formed in a part of a top surface of said first active layer, the fourth semiconductor region being connected to said connection point;
and
a surface wiring configured to connect said high-conductivity region with said fourth semiconductor region.

7 more elements

A power device having high-side and low-side circuits connected in series, a connection point between said high-side and low-side circuits oscillating between predetermined voltage levels, the high-side circuit having a high-side power element and a high-side control circuit for providing a high-side control signal to the high-side power element, the low-side circuit having a low-side power element and a low-side control circuit for providing a low-side control signal independent from the high-side control signal to the low-side power element, higher voltage being applied to the high-side power element than that applied to the low-side power element, the power device comprising:

(a) a first semiconductor chip having the high-side and low side control circuits are merged in, comprising:
a first semiconductor region which acts as a base substrate;
an insulator film formed on top of the first semiconductor region;
a second semiconductor region formed on top of the insulator film so as to form a SOI structure with said first semiconductor region and insulator film, the SOI structure serving as a first capacitor;
element isolation regions dividing said second semiconductor region into dielectrically isolated high-side and low-side active layers, so as to form said high-side control circuit and low-side control circuit therein respectively:
a third semiconductor region, having a conductivity type opposite to that of said first semiconductor region formed in vicinity of a boundary between the first semiconductor region and the insulator film and in a top surface of the first semiconductor region, the third semiconductor region having a specific impurity concentration and diffusion depth so as to develop a large width depletion layer between said third and first semiconductor regions such that a second capacitor being connected between said third and first semiconductor regions, the second capacitor being connected to said first capacitor so that the second capacitor suppresses generation of an inversion layer, which tends to be formed at a bottom of said high-side active layer, said first capacitor being connected between said third and second semiconductor regions;
a groove which starts at a top surface of said high-side active layer and penetrates through said high-side active layer and said insulator film and reaches said third semiconductor region;
a high-conductivity region buried inside the groove,
a fourth semiconductor region formed in a part of a top surface of said high-side active layer, the fourth semiconductor region being connected to said connection point;
and
a surface wiring configured to connect said high-conductivity region with said fourth semiconductor region, and
(b) a second semiconductor chip for merging the high-side power element.

9 more elements

Dependencies are inferred from the claim text.

Facts

Application: 08/828,028Filed 27 Mar 1997
Priority: JP 8-07422528 Mar 1996
Granted: 10 Oct 2000
Term ends: Not estimatedThe source records don’t support an estimate.

Classification7 codes

H10D 30/657
Lateral dmos [ldmos] fets: having substrates comprising insulating layers, e.g. SOI-LDMOS transistors
H10D 10/311
Bipolar junction transistors [BJT]: thin-film BJTs
H10D 12/421
Insulated-gate bipolar transistors [IGBT]: on insulating layers or insulating substrates, e.g. thin-film IGBTs
H10D 86/201
Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless…