Embedded frame buffer system and synchronization method

A method of synchronization of embedded frame buffers for data transfer through a single output comprises the steps of:

• providing multiple embedded memory frame buffer system comprising a master graphics subsystem and a plurality of slave graphics subsystems, each subsystem including a frame buffer and a color palette for decompressing data in the frame buffer, the master subsystem further including a digital to analog converter coupled to receive the decompressed digital data from the palette of each subsystem and outputting analog versions of the digital data to an output device, wherein the multiple embedded memory frame buffer system further includes a timing system for determining which outputs of the subsystems are to be converted by the digital to analog converter at a given time;
• generating a first clock signal and a second clock signal in the master graphics subsystem;
• sending the first and second clock signals to the plurality of slave graphics subsystems;
• and
• delaying the second clock signal to be in phase with a third clock signal generated by a graphics controller such that no data is lost when transferring data from the master and slave graphics subsystems.

A method of synchronization of embedded frame buffers to transfer data through a single output comprising the steps of:

• providing a multiple embedded memory frame buffer system comprising a master graphics subsystem and a plurality of slave graphics subsystems, each subsystem including a frame buffer and a color palette for decompressing data in the frame buffer, the master subsystem further including a digital to analog converter coupled to receive the decompressed digital data from the palette of each subsystem and outputting analog versions of the digital data to an output device, wherein the multiple embedded memory frame buffer system further includes a timing system for determining which outputs of the subsystems are to be converted by the digital to analog converter at a given time;
• sending a reference clock signal to a master graphics subsystem and a slave graphics subsystem;
• and
• generating a first clock signal and a second clock signal in the master graphics subsystem and the slave graphics subsystem which are enabled by the reference clock signal such that the second clock signals of the master and the slave graphics subsystems start on the same cycle of the first clock signals of the master and the slave graphics subsystems.