Flash analog-to-digital converter with reduced number of resistors and comparators
AssigneeSamsung Electronics Co., Ltd.
InventorByoung-kwon An
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Abstract
A flash analog-to-digital converter reduces a property mismatching problem which may occur due to process variations by reducing the number of comparators and resistors as compared to conventional converters. A half code generator receives an analog signal and outputs a one-bit middle code and a (m/2-1)-bit half thermometer code in response to a system clock signal, where m=2.sup.n and n is a positive integer. A code generator receives the middle code and the (m/2-1)-bit half thermometer code, performs a logic operation with respect to the middle code and the half thermometer code, and outputs an operation result as a (m-1)-bit full thermometer code. An encoder encodes the (m-1)-bit full thermometer code into n-bit binary data.
Claims10
An n-bit flash analog-to-digital converter for receiving an analog signal and generating an n-bit binary data in response thereto, said flash analog-to-digital converter comprising:
- a half code generator for receiving the analog signal and outputting a one-bit middle code and a (m/2-1)-bit half thermometer code in response to a system clock signal, wherein m=2.sup.n and n is a positive integer;
- a code generator for receiving the middle code and the (m/2-1)-bit half thermometer code, performing a logic operation with respect to the middle code and the half thermometer code, and outputting an operation result as a (m-1)-bit full thermometer code;
- and
- an encoder for encoding the (m-1)-bit full thermometer code into the n-bit binary data.
An n-bit flash analog-to-digital converter for generating n-bit binary data in response to received analog signals, said flash analog-to-digital converter comprising:
- a half thermometer code generator for receiving first through p-th analog signals via first through p-th input terminals, respectively, and outputting a one-bit middle code and a (m/2-1)-bit half thermometer code, where m=2.sup.n and n is a positive integer, for each of the first through p-th analog signals in response to a system clock signal, wherein p is an integer greater than 1;
- first through p-th channel respective code generators for receiving the middle code and the (m/2-1)-bit half thermometer code, performing a logic operation with respect to the middle code and the half thermometer code, and outputting an operation result as a (m-1)-bit full thermometer code;
- an encoder for encoding the (m-1)-bit full thermometer code into an n-bit binary data;
- and
- first through p-th respective channel encoders for encoding the (m-1)-bit full thermometer code output by respective one of said first through p-th channel code generators into n-bit binary data.
Dependencies are inferred from the claim text.