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AssigneeHitachi, Ltd.
InventorsMasaya Umemura, Hideki Osaka, Toshitsugu Takekuma
Estimating the term…
There are provided plural synchronous RAMs, a memory controller, a bus for inputting the signal output from the memory controller 1a to the synchronous RAMs, and a bus for inputting the signals output from the synchronous RAMs to the memory controller. Each of the buses has a main line and two stub lines connected to the trunk like. Each of the synchronous RAMs is connected to the corresponding stub line so that the sum of the bus length of the bus between the synchronous RAM and the memory controller and the bus length of the bus between the synchronous RAM and the memory controller is substantially constant among all of said synchronous RAMs. Therefore, the signal transmission time between the bus master and the plural bus slaves can be shortened without increasing the number of pins of the bus master while keeping the signal transmission time substantially constant among the plural bus slaves.
A bus system having plural bus slaves, a bus master for controlling said plural bus slaves, a first bus for inputting signals output from said bus master to said bus slaves, and a second bus for inputting signals output from said bus slaves to said bus master,
A printed circuit board on which plural bus slaves and a bus master for controlling said bus slaves are mounted, and a first bus for inputting signals output from said bus master to said bus slaves and a second bus for inputting signals output from said bus slaves to said bus master are formed,
Dependencies are inferred from the claim text.