US 6,125,217 A · Clock distribution network

Abstract

A method and an apparatus for providing an optical clock distribution network. In one embodiment, an optical source is configured to emit optical pulses at a desired clock frequency. The optical pulses are separated into a plurality of split optical pulses, each of which is received by a clock receiver node in a semiconductor die. In one embodiment, each clock receiver node locally generates a photocurrent in response to the split optical beams. Each of the photocurrents is locally converted into voltage and thus into local clock signals, which are used to clock the local area of the integrated circuit. In one embodiment, the semiconductor die includes an additional clock receiver node used to clock a clock generation circuit included in the semiconductor die. The clock generation circuit generates clock signals that are in phase with each other and the other clock signals generated throughout the semiconductor die. In one embodiment, the clock signals generated by the clock generation circuit are used to clock and phase lock input/output communications on the semiconductor die as well as off chip input/output communications between the semiconductor die and other external semiconductor dice of the system.

Claims25

Dependent claims

A clock distribution network, comprising:

a clock receiver node disposed in a first semiconductor die, the clock receiver node providing a first clock signal;
a clock generation circuit disposed in the first semiconductor die, the clock generation circuit coupled to the clock receiver node to generate a second clock signal in phase with the first clock signal to clock a second semiconductor die;
and
a first skew removal circuit included in the clock generation circuit, the first skew removal circuit coupled to the clock receiver node and coupled to a clock input of the second semiconductor die, the first skew removal circuit to generate the second clock signal in response to the first clock signal and a signal of the clock input of the second semiconductor die.

1 more element

A system, comprising:

a first semiconductor die including a clock receiver node disposed therein, the clock receiver node configured to receive clock pulses to generate a first clock signal, the first semiconductor die further including a clock generation circuit disposed therein coupled to the clock receiver node to generate a second clock signal in phase with the first clock signal;
a second semiconductor die having a clock input coupled to the clock generation circuit to receive the second clock signal, the second semiconductor die configured to be clocked by the second clock signal and;
a first skew removal circuit included in the clock generation circuit, the first skew removal circuit coupled to the clock input of the second semiconductor die and coupled to the clock receiver node, the first skew removal circuit to generate the second clock signal in response to the first clock signal and a signal of the clock input of the second semiconductor die.

Dependencies are inferred from the claim text.

Clock distribution network

Life of this patent

Clock distribution network

Life of this patent

Abstract

Claims25