# US 6,125,059 A · Method for erasing nonvolatile memory cells in a field programmable gate array

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- Number: US 6,125,059 A
- Document ID: US6125059A
- Status: Granted
- Kind: A
- Application number: 09/311,975
- Filed: 1999-05-14
- Granted: 2000-09-26
- Earliest claimed: 1999-05-14
- Assignees: GateField Corporation
- Inventors: Volker Hecht
- Web page: https://patentgrep.com/patent/US6125059A

## CPC

- G11C 16/14: Circuits for erasing electrically, e.g. erase voltage switching circuits
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

In an FPGA, nonvolatile reprogrammable interconnect cells which have a switch transistor and at least one second transistor for programming and sensing, or a second transistor for sensing and a buried N+ region for programming the cell, use a high voltage on the common control gate for the cell erasing operation. The source/drains of the switch transistor are grounded. By placing an intermediate voltage on the source/drains of the second transistor, erase times can be reduced and test costs can be significantly lowered.

## Claims

### Claim 1

In an integrated circuit having a plurality of programmable interconnect cells, each cell selectively interconnecting first and second circuit nodes, each cell having a first transistor having a floating gate, a control gate, and first and second source/drain regions connected respectively to said first and second circuit nodes, and a second transistor having a floating gate connected to said floating gate of said first transistor, a control gate connected to said control gate of said first transistor, and first and second source/drain regions, a method of erasing said programmable interconnect cells comprising
asserting a first voltage of a first polarity on said control gates of said first and second transistors;
asserting a ground voltage on said first and second source/drain regions of said first transistor; and
asserting a second voltage intermediate said first voltage and said ground voltage on said first and second source/drain regions of said second transistor.

### Claim 2 (depends on 1)

The method of claim 1 wherein each of said programmable interconnect cells further has a tunneling device having a floating gate connected to said floating gates of said first and second transistors, a control gate connected to said control gates of said first and second transistors, and a conductive region below said floating and said control gate, said method further comprising
asserting a third voltage intermediate said first voltage and said ground voltage on said conductive region of said tunneling device.

### Claim 3 (depends on 2)

The method of claim 2 wherein said third voltage is equal to said second voltage.

### Claim 4 (depends on 2)

The method of claim 2 wherein said first voltage is approximately +18 volts and said second and third voltages are in the range of 0 to +12 volts.

### Claim 5 (depends on 1)

The method of claim 1 wherein said first voltage is approximately +18 volts and said second voltage is in the range of 0 to +12 volts.