High availability computer system and methods related thereto

A gated balanced clock tree circuit that automatically and selectively supplies clock pulses to the logical flip-flops (F/Fs) of an application specific integrated circuit (ASIC) comprising:

• a clock trunk in which flows the clock pulses to the logical F/Fs of the ASIC, the clock tree having a plurality of branches extending therefrom;
• at least one AND gate being disposed in at least one of the branches of the clock trunk feeding at least some of the logical F/Fs;
• control circuitry that controls each of the at least one AND gate so at least some of the logical F/Fs are fed only certain clock pulses;
• and
• wherein said control circuitry is configured so the AND gate automatically allows clock pulses to be feed to the at least some of logical F/Fs during a first operational condition of a computer system using the ASIC and wherein said control circuitry is also configured so clock pulses are automatically blocked by the AND gate when in a second operational condition of the computer system.

A gated balanced clock tree circuit that automatically and selectively supplies clock pulses to the logical flip-flops (F/Fs) of an application specific integrated circuit (ASIC) comprising:

• a clock trunk in which flows the clock pulses to the logical F/Fs of the ASIC, the clock tree having a plurality of branches extending therefrom;
• at least one AND gate being disposed in at least one of the branches of the clock trunk feeding at least some of the logical F/Fs;
• control circuitry that controls each of the at least one AND gate so at least some of the logical F/Fs are fed only certain clock pulses;
• wherein said control circuitry is configured so the AND gate automatically allows clock pulses to be feed to the at least some of logical F/Fs during a first operational condition of a computer system using the ASIC and wherein said control circuitry is also configured so clock pulses are automatically blocked by the AND gate when in a second operational condition of the computer system;
• a phased locked loop device (PLL) that controls the clock signals being fed into the clock trunk;
• a delay cell being electrically interconnected to said PLL and a selected branch of said clock tree, wherein the delay cell delays each clock pulse from the selected branch of the clock tree by a predetermined amount for deskewing the clock pulses to the logical F/Fs;
• and
• wherein the clock pulses through the selected branch are not blocked from going to the PLL when in the second operational condition of the computer system.

A method for controlling clock pulses to logical flip-flop (F/Fs) of an application specific integrated control circuit (ASIC) comprising the steps of:

• providing an ASIC having a gated balanced clock tree circuit that automatically and selectively distributes clock pulses to the logical F/Fs, the clock tree having a plurality of branches therefrom;
• configuring the gated balance clock tree circuit so clock pulses are distributed to at least some of the logical F/Fs when a computer system is in a first operational condition;
• and
• re-configuring the gated balance clock tree circuit to block the distribution of the clock pulses to the at least some of the logical F/Fs when the computer system is in a second operational condition.

A method for controlling clock pulses to logical flip-flops F/Fs) of an application specific integrated control circuit (ASIC) comprising the steps of:

• providing an ASIC having a gated balanced clock tree circuit that automatically and selectively distributes clock pulses to the logical F/Fs, the clock tree having a plurality of branches therefrom, the gated balance clock tree circuit including a phased locked loop device (PLL) that controls the clock signals being fed into the clock trunk;
• configuring the gated balance clock tree circuit so clock pulses are distributed to at least some of the logical F/Fs when a computer system is in a first operational condition;
• re-configuring the gated balance clock tree circuit to block the distribution of the clock pulses to the at least some of the logical F/Fs when the computer system is in a second operational condition;
• feeding back clock pulses to the PLL from a selected branch of the clock tree circuit;
• delaying the clock pulses being feedback a predetermined amount for deskewing the clock pulses to the logical F/Fs;
• and
• wherein the clock pulses being feed back are not blocked from going to the PLL when in the second operational condition of the computer system.

A system to supply clock pulses in a computer system comprising:

• at least first and second clock generation and distribution devices, where the first clock generation and distribution device is set as the source for clock pulses being supplied by the system;
• wherein each of the first and second clock generation and distribution devices includes:
• primary oscillator circuitry being electrically configured so as to generate periodic signal pulses,
• detection circuitry being configured electrically to monitor the periodic pulses generated by the oscillator circuitry to detect a failure of that circuitry, and
• signal generating circuitry, responsive to the detection circuitry, that is configured to provide an output signal representative of the detection of a failure of the oscillator circuitry;
• and
• clock pulse failover circuitry that is configured so the clock supply system automatically redesignates the source of clock pulses being supplied as the second clock generation and distribution device responsive to a failure signal from the signal generating circuitry of the first clock generation and distribution device.

A high availability scalable multiprocessor computer system, comprising:

• a backplane, including at least one backplane communication bus and a diagnostic bus;
• a plurality of motherboards, detachably connected to said backplane;
• each motherboard interfacing to said at least one backplane communication bus and to said diagnostic bus, each of said plurality of motherboards including:
• at least one backplane communication bus interface mechanism interfacing at least one of said plurality of motherboards to said at least one backplane communication bus;
• a memory system including main memory distributed among said plurality of motherboards, directory memory for maintaining main memory coherency with caches on other motherboards, and a memory controller module for accessing said main memory and directory memory and interfacing to said motherboard communication bus;
• at least one daughterboard, detachably connected to said motherboard and interfacing to said motherboard communication bus, said at least one daughterboard further including:
• a motherboard communication bus interface module, for interfacing said at least one daughterboard to said motherboard communication bus and a local bus on said daughterboard;
• and
• at least one cache memory system including cache memory and a cache controller module maintaining said cache memory for a processor of said scalable multiprocessor computer system;
• a backplane diagnostic bus interface mechanism interfacing each of said plurality of motherboards to said backplane diagnostic bus;
• a microcontroller for processing information and providing outputs;
• and
• a test bus controller mechanism including registers therein;
• a scan chain that electrically interconnects functionalities mounted on each motherboard and each of said at least one daughter board to said test bus controller;
• and
• an applications program for execution with said microcontroller, said applications program including instructions and criteria to automatically test the functionalities and electrical connections and interconnections, to automatically determine the presence of a faulted component and to automatically functionally remove the faulted component from the computer system.