Digital clock recovery circuit with phase interpolation

A digital clock recovery circuit comprising:

• a phase detector having a first input, a second input, a first output, and a second output, wherein the first input is configured to receive a data signal;
• a digital filter having a first input, a second output, a first output, and a second output, wherein the first input and the second input of the digital filter are connected to the first output and the second output of the phase detector;
• a phase selection unit having a first input, a second input, a third input, and an output, wherein the first input and the second input of the phase selector are connected to the first output and the second output of the digital filter and wherein the output of the phase selection unit is connected to the second input of the phase detector;
• a frequency synthesizer having an input and an output, wherein the input of the frequency synthesizer is configured to receive a timing reference signal and wherein the frequency synthesizer creates a first number clock output signals at the output, each clock output signal having a phase difference from another output clock signal within the first number of clock output signals, wherein a first number of clock phases for the plurality of clock output signals are generated;
• and
• a phase interpolation unit having an input and an output, the input of the phase interpolation unit being connected to the output of the frequency synthesizer and the output of the phase interpolation unit being connected to the third input of the phase selection unit, wherein the phase interpolation unit increases the first number of clock output signals generated by the frequency synthesizer to generate a second number of clock output signals, each clock output signal in the second number of clock output signals having a phase difference from another output clock signal within the second number of clock output signals and wherein the phase selection unit selects a clock output signal from the second number of clock output signals.

An apparatus for recovering a clock signal, the apparatus comprising:

• reception means for receiving a reference clock signal;
• clock generation means for generating a plurality of clock signals from the reference clock signal using a ring oscillator having a plurality of phases with a first phase difference between phases within the plurality of phases;
• interpolation means for interpolating the plurality of clock signals to generate a second plurality of clock signals, wherein the second plurality of clock signals has a second plurality of phases with a second phase difference between phases within the plurality of phases;
• and
• selection means for selecting a clock signal from the second plurality of clock signals, wherein the clock signal forms a recovered clock signal.

A clock recovery circuit comprising:

• a plurality of delay cells coupled in series and having an input and an output, the input being connected to a first of the plurality of delay cells, the input being configured to receive a reference clock signal, wherein the plurality of delay cells generate a plurality of clock signals having a plurality of phases at the output;
• phase interpolation means having an input and an output, the input of the phase interpolation means being coupled to the output of the plurality of delay cells, wherein the phase interpolation means generates a second plurality of clock signals having a second plurality of phases at the output of the phase interpolation means;
• and
• phase selection means for selecting a clock signal from the plurality of clock signals.