High frequency switch device, front end unit and transceiver

A front end unit used at a radio frequency stage of a transceiver and having a high frequency switch device as a radio frequency switch, the high frequency switch device comprising:

• first, second and third terminals;
• a first circuit composed of a first FET, and a first inductor and a first capacitor both connected with said first FET in parallel to each other, one end of said first circuit being connected to said first terminal;
• and
• a second circuit composed of a second FET, and a second inductor and a second capacitor both connected with the second FET in parallel to each other, one end of said second circuit being connected to said first circuit and the other end of said second circuit being connected to said second terminal, and
• wherein a first control signal is applied to a gate of the first FET via a resistance;
• a second control signal is applied to a gate of the second FET via a resistance;
• said third terminal is connected to a common junction point of said first and second circuits;
• and a predetermined potential is applied to the common junction point.

A transceiver having a high frequency switch device for switching radio signal paths when radio signals are given from a transmitter to an antenna or when radio signals are given from the antenna to a receiver, the high frequency switch device comprising:

• first, second and third terminals connected to the transmitter, the receiver and the antenna, respectively;
• a first circuit composed of a first FET, and a first inductor and a first capacitor both connected with said first FET in parallel to each other, one end of said first circuit being connected to said first terminal;
• and
• a second circuit composed of a second FET, and a second inductor and a second capacitor both connected with the second FET in parallel to each other, one end of said second circuit being connected to said first circuit and the other end of said second circuit being connected to said second terminal, and
• wherein a first control signal is applied to a gate of the first FET via a resistance;
• a second control signal is applied to a gate of the second FET via a resistance;
• said third terminal is connected to a common junction point of said first and second circuits;
• and a predetermined potential is applied to the common junction point.