Computer system controller having internal memory and external memory control
AssigneeMemtrax LLC
InventorNeal Margulis
Life of this patent
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Abstract
The present invention relates generally to an optimized memory architecture for computer systems and, more particularly, to integrated circuits that implement a memory subsystem that is comprised of internal memory and control for external memory. The invention includes one or more shared high-bandwidth memory subsystems, each coupled over a plurality of buses to a display subsystem, a central processing unit (CPU) subsystem, input/output (I/O) buses and other controllers. Additional buffers and multiplexers are used for the subsystems to further optimize system performance.
Claims26
A computer system having a common display memory and main memory, comprising:
- a display;
- an internal memory subsystem and an external memory subsystem;
- a plurality of multi-use memory channels coupled to said memory subsystems;
- a plurality of processor and/or peripheral subsystems;
- a memory channel data switch and controller unit for dynamically allocating the multi-use memory channels among the plurality of processor and/or peripheral subsystems;
- a central processing unit (CPU) subsystem controller unit producing output signals to be applied to the memory channel data switch and controller unit;
- a graphics/drawing and display subsystem producing output signals to be applied to the memory channel data switch and controller unit;
- and
- an arbitration and control unit producing output signals to be applied to the CPU subsystem controller unit and to the graphics/drawing and display subsystem.
A computer system comprising:
- a display;
- a common memory architecture including
- a display memory,
- a main memory, and
- a plurality of internal and external memory subsystems, each memory subsystem having its own multi-use memory channel;
- a plurality of processor and/or peripheral subsystems;
- a memory channel data switch and controller unit wherein one multi-use memory channel is dynamically allocatable to each processor and/or peripheral subsystem;
- a central processing unit (CPU) subsystem controller unit producing output signals received proportionally by the memory channel data switch and controller unit;
- and
- an arbitration and control unit producing output signals received proportionally by the CPU subsystem controller unit.
A computer system comprising:
- a plurality of internal memory subsystems and external memory subsystems wherein at least one of the internal memory subsystems includes DRAM memory;
- multiple concurrently accessible multi-use memory channels;
- a graphics controller;
- a display processor subsystem;
- a plurality of processor and/or peripheral subsystems;
- a memory channel data switch and controller unit wherein one multi-use memory channel is dynamically allocatable to each processor and/or peripheral subsystem;
- means for the processor and/or peripheral subsystems to access a common memory region.
A method for correcting a computer system comprising the steps of:
- providing a display;
- providing a common display memory and main memory, the common memory including,
- an internal memory subsystem,
- an external memory subsystem, and
- a plurality of multi-use memory channels coupled to the memory subsystems;
- using a central processing unit (CPU) subsystem controller unit producing output signals to allocate the internal memory subsystem and the external memory subsystem through the multi-use memory channels;
- using a graphics/drawing and display subsystem to provide signals to the display;
- and
- inputting a plurality of output signals from the CPU subsystem controller unit to an arbitration and control unit producing output signals to be applied to the CPU subsystem controller unit and to the graphics/drawing and display subsystem.
Dependencies are inferred from the claim text.