Multi-core chip providing external core access with regular operation function interface and predetermined service operation services interface comprising core interface units and masters interface unit

A data processing system, comprising:

• (a) a processing unit coupled to a storage unit through a bus;
• and
• (b) an integrated circuit device disposed in one of the processing and storage units, the integrated circuit device including:
• (1) a plurality of cores;
• (2) a function interface coupling at least one of the plurality of cores to a function access port to permit external data transfer with the integrated circuit device during regular operation thereof;
• and
• (3) a service interface coupling the plurality of cores to a service access port to permit external data transfer with the integrated circuit device in connection with a predetermined service operation responsive to a request received over the service interface, the service interface including:
• (i) a plurality of core interface units integrated with the plurality of cores on the integrated circuit device, each core interface unit coupled to a core from the plurality of cores;
• and
• (ii) a master interface unit integrated with the plurality of cores on the integrated circuit device, the master interface unit coupled between the service access port and the plurality of core interface units and configured to request at least a selected one of the plurality of core interface units to initiate execution of the predetermined service operation.

A method of accessing a plurality of interconnected cores disposed on an integrated circuit device of the type including a function interface coupling at least one of the plurality of cores to a function access port to permit external data transfer with the integrated circuit device during regular operation thereof, the method comprising:

• (a) receiving a service request through a service access port separate from the function interface and coupled to a master interface unit integrated with the plurality of cores on the integrated circuit device;
• (b) generating in response to the service request a first predetermined signal to at least a selected one of a plurality of core interface units integrated with the plurality of cores on the integrated circuit device;
• and
• (c) performing a predetermined service operation with the selected core interface unit-in response to the first predetermined signal.

A method of retrieving status information from a plurality of core interface units integrated with a plurality of interconnected cores disposed on an integrated circuit device, the plurality of core interface units coupled to one another and a master interface unit through a core interface bus, the method comprising:

• (a) issuing a request to each core interface unit with the master interface unit;
• (b) for each core interface unit, outputting a status bit to the master interface unit over a unique line in the core interface bus in response to the request;
• and
• (c) polling the unique lines in the core interface bus with the master interface unit.

A program product, comprising:

• (a) a hardware definition program that defines a service interface circuit arrangement configured to be integrated with a plurality of cores and a function interface on an integrated circuit device, the function interface configured to couple at least one of the plurality of cores to a function access port to permit external data transfer with the integrated circuit device during regular operation thereof, the service interface circuit arrangement configured to couple the plurality of cores to a service access port to permit external data transfer with the integrated circuit device in connection with a predetermined service operation responsive to a request received over the service interface, the service interface including:
• (i) a plurality of core interface unit circuit arrangements configured to be integrated with the plurality of cores on the integrated circuit device, each core interface unit circuit arrangement configured to be coupled to a core from the plurality of cores;
• and
• (ii) a master interface unit circuit arrangement configured to be integrated with the plurality of cores on the integrated circuit device, the master interface unit circuit arrangement configured to be coupled between the service access port and the plurality of core interface unit circuit arrangements and to request at least a selected one of the plurality of core interface unit circuit arrangements to initiate execution of the predetermined service operation;
• and
• (b) a signal bearing media bearing the hardware definition program.

An integrated circuit device, comprising:

• (a) a plurality of cores disposed on the integrated circuit device;
• (b) a function interface coupling at least one of the plurality of cores to a function access port to permit external data transfer with the integrated circuit device during regular operation thereof;
• and
• (c) a service interface coupling the plurality of cores to a service access port to permit external data transfer with the integrated circuit device in connection with a predetermined service operation, the service interface including:
• (1) a plurality of core interface units integrated with the plurality of cores on the integrated circuit device, each core interface unit coupled to a core from the plurality of cores;
• and
• (2) a master interface unit integrated with the plurality of cores on the integrated circuit device, the master interface unit coupled between the service access port and the plurality of core interface units and configured to request at least a selected one of the plurality of core interface units to initiate execution of the predetermined service operation;
• wherein at least a portion of the core interface units are daisy chained core interface units coupled to one another in a daisy chain arrangement, with each daisy chained core interface unit coupled to provide a daisy chain signal to a next daisy chained core interface unit and thereby initiate a predetermined operation in the next daisy chained core interface unit, and wherein the plurality of core interface units includes a sequence master core interface unit, the sequence master core interface unit configured to initiate the predetermined operations in the daisy chain arrangement of core interface units in response to a sequence initiation signal.

An integrated circuit device, comprising:

• (a) a plurality of cores disposed on the integrated circuit device;
• (b) a function interface coupling at least one of the plurality of cores to a function access port to permit external data transfer with the integrated circuit device during regular operation thereof;
• and
• (c) a service interface coupling the plurality of cores to a service access port to permit external data transfer with the integrated circuit device in connection with a predetermined service operation, the service interface including:
• (1) a plurality of core interface units integrated with the plurality of cores on the integrated circuit device, each core interface unit coupled to a core from the plurality of cores;
• (2) a master interface unit integrated with the plurality of cores on the integrated circuit device, the master interface unit coupled between the service access port and the plurality of core interface units and configured to request at least a selected one of the plurality of core interface units to initiate execution of the predetermined service operation;
• and
• (3) a core interface bus coupled between the master interface unit and each of the plurality of core interface units, wherein each core interface unit has a unique address on the bus, wherein each core interface unit is configured to output at least one status bit over the bus in response to a signal generated by the master interface unit, wherein the bus includes a plurality of lines, and wherein each core interface unit is mapped to a unique line from the bus based upon the address thereof such that each core interface unit outputs the status bit therefor over the unique line therefor in response to the status request signal.

An integrated circuit device, comprising:

• (a) a plurality of cores disposed on the integrated circuit device, a first core among the plurality of cores including a plurality of arrays, each array including an engine;
• (b) a function interface coupling at least one of the plurality of cores to a function access port to permit external data transfer with the integrated circuit device during regular operation thereof;
• and
• (c) a service interface coupling the plurality of cores to a service access port to permit external data transfer with the integrated circuit device in connection with a predetermined service operation, the service interface including:
• (1) a plurality of core interface units integrated with the plurality of cores on the integrated circuit device, each core interface unit coupled to a core from the plurality of cores, a first core interface unit from the plurality of core interface units coupled to the first core, the first core interface unit including an array built-in self-test (ABIST) controller coupled to the engine in each of the plurality of arrays in the first core, wherein the ABIST controller is configured to monitor completion and status of an ABIST operation on each engine;
• and
• (2) a master interface unit integrated with the plurality of cores on the integrated circuit device, the master interface unit coupled between the service access port and the plurality of core interface units and configured to request at least a selected one of the plurality of core interface units to initiate execution of the predetermined service operation;
• wherein each operational engine in each of the plurality of arrays is configured to output a done signal to the ABIST controller upon completion of an ABIST operation, and wherein the ABIST controller includes a done mask that filters done signals from non-operational engines to determine when all operational engines have completed the operation.