US 6,112,218 AGranted

Digital filter with efficient quantization circuitry

AssigneeTexas Instruments Incorporated

InventorsPrashant Gandhi, James R. Hochschild

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Abstract

An infinite impulse response (IIR) digital filter and method of performing the same is disclosed. The digital filter may be realized by way of a programmable logic device, such as a digital signal processor (75), or alternatively by way of dedicated logic including adders (44, 48, 50, 54, 58, 62, 66, 70, 72) and shifters (46, 52, 56, 60, 64). In either case, addition operations (34) are interleaved among first and second output sample values (y.sub.n-1, y.sub.n-2), so that the resulting addition (30; 72; 215; 320) may be carried out with adder circuitry of the same precision as the signal input (x.sub.n) and signal output (y.sub.n). Carry control circuitry (76, 78, 80, 82, 84, 88; 217; 317) is provided to efficiently incorporate magnitude truncation quantization.

Claims19

Dependent claims

A method of determining a feedback value in a digital filter, the feedback value corresponding to a sum of first and second products, the first product corresponding to a first coefficient value times a first output sample value, and the second product corresponding to a second coefficient value times a second output sample value, comprising the steps of:

applying a least significant digit of the first coefficient value to the first output sample value to produce a first partial sum in a sequence of partial sums;
adding the first partial sum to a value determined by applying a least significant digit of the second coefficient value to the second output sample value, to produce a next partial sum in the sequence of partial sums;
shifting the next partial sum according to a difference in order between the least significant digit of the second coefficient value and a next digit of the first coefficient value to produce a shifted next partial sum, and a fractional portion comprised of one or more of least significant bits of the next partial sum;
after the shifting step, adding the shifted next partial sum to a value determined by applying the next digit of the first coefficient value to the first output sample value to produce another next partial sum in the sequence of partial sums;
successively performing the adding, shifting, and adding steps according to the first and second coefficient values, to produce a final partial sum in the sequence of partial sums;
and
generating the feedback value based upon the final partial sum.

4 more elements

An electronic system, comprising:

a signal source for generating digital signals;
and
a digital filter, coupled to the signal source, for filtering the digital signals generated by the signal source, by performing a sequence of operations comprising:
applying a least significant digit of the first coefficient value to the first output sample value to produce a first partial sum in a sequence of partial sums;
adding the first partial sum to a value determined by applying a least significant digit of the second coefficient value to the second output sample value, to produce a next partial sum in the sequence of partial sums;
shifting the next partial sum according to a difference in order between the least significant digit of the second coefficient value and a next digit of the first coefficient value to produce a shifted next partial sum, and a fractional portion comprised of one or more of least significant bits of the next partial sum;
after the shifting step, adding the shifted next partial sum to a value determined by applying the next digit of the first coefficient value to the first output sample value to produce another next partial sum in the sequence of partial sums;
successively performing the adding, shifting, and adding steps according to the first and second coefficient values, to produce a final partial sum in the sequence of partial sums;
and
generating the feedback value based upon the final partial sum.

7 more elements

An electronic device, comprising:

a memory for storing instruction codes, input sample values, and output sample values;
a controller, for receiving instruction codes from the memory and for generating control signals based thereupon;
and
a datapath, coupled to the controller, for executing a sequence of instructions responsive to the control signals from the controller, the sequence of instructions comprising:
retrieving first and second coefficient values and first and second output sample values from the memory;
applying a least significant digit of the first coefficient value to the first output sample value to produce a first partial sum in a sequence of partial sums;
adding the first partial sum to a value determined by applying a least significant digit of the second coefficient value to the second output sample value, to produce a next partial sum in the sequence of partial sums;
shifting the next partial sum according to a difference in order between the least significant digit of the second coefficient value and a next digit of the first coefficient value to produce a shifted next partial sum, and a fractional portion comprised of one or more of least significant bits of the next partial sum;
after the shifting step, adding the shifted next partial sum to a value determined by applying the next digit of the first coefficient value to the first output sample value to produce another next partial sum in the sequence of partial sums;
successively performing the adding, shifting, and adding steps according to the first and second coefficient values, to produce a final partial sum in the sequence of partial sums;
and
generating a feedback value based upon the final partial sum.

9 more elements

Dependencies are inferred from the claim text.