US 6,112,019 AGranted

Distributed instruction queue

AssigneeGeorgia Tech Research Corporation

InventorsJoseph I. Chamdani, Cecil O. Alford

Life of this patent

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Abstract

A distributed instruction queue (DIQ) in a superscalar microprocessor supports multi-instruction issue, decoupled data flow scheduling, out-of-order execution, register renaming, multi-level speculative execution, and precise interrupts. The DIQ provides distributed instruction shelving without storing register values, operand value copying, and result value forwarding, and supports in-order issue as well as out-of-order issue within its functional unit. The DIQ allows a reduction in the number of global wires and replacement with private-local wires in the processor. The DIQ's number of global wires remains the same as the number of DIQ entries and data size increases. The DIQ maintains maximum machine parallelism and the actual performance of the microprocessor using the DIQ is better due to reduced cycle time or more operations executed per cycle.

Claims22

Dependent claims

A distributed instruction queue comprising:

at least two entry cells, each of said at least two entry cells being capable of holding a decoded instruction corresponding to at least one source operand, said at least one source operand for each decoded instruction being stored in storage means external to said distributed instruction queue, said at least one source operand not being copied into said distributed instruction queue;
an allocate port connected to said at least two entry cells for allocation of decoded instructions to said entry cells without reading the at least one source operand corresponding to each of the decoded instructions;
and
an issue port connected to said at least two entry cells for issuance of decoded instructions under logic control in any order from said entry cells to a functional unit external to said distributed instruction queue after such time as all of the source operands corresponding to the decoded instruction to be issued are available in the external storage means, the source operands being read from the external storage means at such time as the decoded instruction is issued, and wherein no result value is forwarded from the functional unit to said distributed instruction queue.

1 more element

Dependencies are inferred from the claim text.

Facts

Application: 08/489,509Filed 12 Jun 1995
Granted: 29 Aug 2000
Term ends: Not estimatedThe source records don’t support an estimate.

Classification7 codes

G06F 9/3836
Concurrent instruction execution, e.g. pipeline or look ahead: instruction issuing, e.g. dynamic instruction scheduling or out of order…
G06F 9/3838
Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution: dependency mechanisms, e.g. register scoreboarding
G06F 9/384
Dependency mechanisms, e.g. register scoreboarding: register renaming
G06F 9/3854
Concurrent instruction execution, e.g. pipeline or look ahead: instruction completion, e.g. retiring, committing or graduating