Method and apparatus for adjusting control signal timing in a memory device

A memory device operable to transfer data to and from a device external to the memory device, the memory device receiving a clock signal controlling timing of data transfer operations, the memory device comprising:

• a memory array operable to store data;
• a data input circuit operable to receive data from the external device;
• a data output circuit operable to provide data to the external device;
• an array access circuit coupled with the memory array and with the data input and output circuits, the array access circuit operable to transfer data from the data input circuit to the memory array for storage therein, the array access circuit further operable to transfer data stored in the memory array to the data output circuit;
• a memory control circuit operable to produce a plurality of control signals, each applied to a corresponding one of the array access, data input, and data output circuits to control operation thereof;
• a clock sensing circuit operable to receive the clock signal and to responsively produce a speed signal having a value corresponding to a frequency of the clock signal;
• and
• a control signal delay circuit coupled between the memory control circuit and one of the array access, data input, and data output circuits, the control signal delay circuit operable to receive the speed signal and to responsively delay one of the control signals applied to the one of the array access, data input, and data output circuits.

A computer system, comprising:

• a data input device;
• a data output device;
• and
• computer circuitry coupled with the data input and data output devices and including a memory device receiving a clock signal, the memory device having:
• a memory array operable to store data;
• a memory control circuit operable to produce a plurality of control signals controlling access to the memory array;
• and
• a control signal timing circuit coupled with the memory control circuit and operable to receive the clock signal and one of the control signals, the control signal timing circuit delaying the one of the control signals by a time-delay amount corresponding to the frequency of the clock signal.

In an integrated circuit adapted to receive a clock signal and to perform internal operations including producing a control signal, a method of controlling timing of the control signal, comprising the steps of:

• sensing the frequency of the clock signal;
• receiving the control signal;
• and
• delaying the control signal by an amount corresponding with the sensed frequency of the clock signal.

A method of sensing the frequency of a clock signal, comprising the steps of:

• comparing the period of the clock signal to a plurality of time intervals;
• for each of the time intervals that the period of the clock signal exceeds, producing a respective one of a plurality of interval indicating signals;
• and
• producing a clock speed signal having a value corresponding with the combination of interval indicating signals.