Fast charge and thermal asperity compensation circuit

A circuit for reading stored data in accordance with variations in resistance of a magneto-resistive head, said circuit comprising:

• a differential amplifier having a pair of parallel differential amplifier paths;
• means for coupling a magneto-resistive head across said differential paths;
• means for coupling a dc bias to said differential amplifier paths for applying a dc bias current to said head to thereby produce data signals in said differential amplifier paths responsive to variations in head resistance due to its sensing of stored data, said bias current providing a dc voltage offset between said differential paths;
• an amplifier connected to said differential amplifier for amplifying and delivering the differential signals thereof to an output of said amplifier;
• a feedback loop coupled to said output and to said differential amplifier for controlling said differential amplifier in a manner to reduce the dc voltage offset therein during activation, and said feedback loop further includes a thermal asperity compensator having a signal generator and a threshold detector, said threshold detector being coupled to said output and configured for triggering said signal generator for producing a predetermined signal when the magnitude of the voltage differential in said output exceeds a given threshold value, and said feedback loop further includes means responsive to said predetermined signal for increasing the ac gain of at least a portion of said feedback loop to thereby raise the lower corner frequency of the differential amplifier and filter out the relatively low frequency of the thermal asperity waveform.

A circuit for reading stored data in accordance with variations in resistance of a magneto-resistive head, said circuit comprising:

• a differential amplifier having a pair of parallel differential amplifier paths;
• means for coupling a magneto-resistive head across said differential amplifier paths;
• means for coupling a dc bias to said differential amplifier paths for applying a dc bias current to said head so as to produce data signals in said differential amplifier paths responsive to variations in head resistance due to its sensing of stored data, said bias current providing a dc voltage offset between said differential paths;
• a dc capacitor coupled between said differential paths in parallel to said means for coupling said head across said differential paths so as to essentially eliminate said dc voltage offset therein when said capacitor is fully charged;
• a feedback loop configured for evaluating the differential voltage between said differential paths and for controlling the current therein to reduce the dc voltage offset there between such that said capacitor is rapidly brought to a fully charged condition upon activation of said circuit.