Fast and compact address bit routing scheme that supports various DRAM bank sizes and multiple interleaving schemes

A method of implementing multi-cache interleaving by converting an m bit address generated by a processor in a computer system to bank bits, row bits, and l column bits used to access a main memory system of the computer system that is 2.sup.h bytes wide, wherein address bits of the m bit address are arranged in ascending order from a least significant 0 address bit to a most significant m-1 address bit, the computer system also includes a cache memory that holds a subset of contents of the main memory, with the cache memory organized into a series of cache lines and each cache line is 2.sup.q bytes wide, the method comprising:

• generating a first set of one or more bank bits based on one or more address bits more significant than the q address bit and less significant than the h+l-1 address bit;
• mapping a column bit to each address bit more significant than the h-1 address bit and less significant than the q+1 address bit;
• mapping one or more column bits to address bits more significant than the q address bit and less significant that h+1 address bit;
• and
• mapping row bits to address bits.

A method of mapping n address bits provided by a processor to rank, bank, row, and column bits required to access a main memory unit, the method comprising:

• accessing a routing register for each of the n address bits to retrieve a routing encoding;
• routing each address bit to a bank bit, row bit, or column bit based on the routing encoding accessing an address-to-rank select register for each rank bit to be generated, wherein the address-to-rank select register identifies address bits to be considered when generating a rank bit associated with the address-to-rank select register;
• accessing an address-to-rank select register for each rank bit to be generated, wherein the address-to-rank select register identifies address bits to be considered when generating a rank bit associated with the address-to-rank select register;
• accessing an address-to-rank value register for each rank bit to be generated, wherein the address-to-rank value register indicates values required to be found at address bits that are selected to be considered when generating a rank bit associated with the address-to-rank select register and the address-to-rank value register;
• and
• asserting each rank bit if the values of the address bits selected by the address-to-rank select register associated with the rank bit match the corresponding values stored in the address-to-rank value register associated with the rank bit.

A computer system comprising:

• a processor that generates an m bit address to facilitate memory accesses, wherein address bits of the m bit address are arranged in ascending order from a least significant 0 address bit to a most significant m-1 address bit;
• a main memory unit that is 2.sup.h bytes wide and comprises memory sockets that supports memory modules that are addressed via j bank bits, k row bits, and at least l and no more than p column bits, wherein p is greater than l+1;
• and
• a memory controller coupled between the main memory unit and the processor, wherein the memory controller includes a reduced routing function that routes an address bit more significant than the l+h bit and less significant than the p+h bit to one member of a reduced set comprising at least one and less than j bank bits, at least one and less than j bank bits, and at least one and less than p column bits.

A computer system comprising:

• a processor that generates an m bit address to facilitate memory accesses, wherein address bits of the m bit address are arranged in ascending order from a least significant 0 address bit to a most significant m-1 address bit;
• a cache memory coupled to the processor, the cache memory holding a subset of contents of the main memory unit, wherein the cache memory is organized into a sets of cache lines that are addressed by an index portion of the address, and a tag portion of the address is associated with each cache line;
• a main memory unit that is 2.sup.h bates wide and is addressed via j bank bits, k row bits, and column bits;
• and
• a memory controller coupled between the main memory unit and the cache memory, wherein the memory controller includes a reduced routing function that routes an address bit from the tag portion of the address to one member of a reduced set comprising at least one and less than j bank bits and at least one and less than j bank bits.

A computer system comprising:

• a processor that generates an address at least 32 bits wide to facilitate memory accesses;
• a cache memory coupled to the processor, the cache memory holding a subset of contents of the main memory unit, wherein the cache memory is organized into a sets of cache lines that are addressed by an index portion of the address, and a tag portion of the address is associated with each cache line;
• a main memory unit that is 2.sup.h bytes wide and comprises memory sockets that support memory modules that are addressed via up to 3 bank bits, between k and k+3 row bits, inclusive, and between l and l+3 column bits, inclusive;
• and
• a memory controller coupled between the main memory unit and the cache memory, wherein the memory controller includes a plurality of reduced routing functions that route a corresponding plurality of address bits such that no encoding for a reduced routing function requires more than 3 bits, and the memory controller implements at least two interleaving strategies from the set of:
• multi-cache interleaving, cache effect interleaving, and page interleaving.