Amplifier having improved common mode voltage range

An amplifier having an improved common-mode voltage range, said apparatus comprising:

• a first P-channel transistor having a gate, a source and a drain;
• a first N-channel transistor having a gate, a source and a drain coupled to said first P-channel transistor wherein the source of said first N-channel transistor is coupled to the drain of said first P-channel transistor and the drain of said first N-channel transistor is coupled to the source of said first P-channel transistor;
• a second P-channel transistor having a gate, a source and a drain;
• a second N-channel transistor having a gate, a source and a drain coupled to said second P-channel transistor wherein the source of said second N-channel transistor is coupled to the drain of said second P-channel transistor and the drain of said second N-channel transistor is coupled to the source of said second P-channel transistor;
• a third P-channel transistor having a gate, a source and a drain;
• a third N-channel transistor having a gate, a source and a drain coupled to said third P-channel transistor wherein the source of said third N-channel transistor is coupled to the drain of said third P-channel transistor and the drain of said third N-channel transistor is coupled to the source of said third P-channel transistor;
• a fourth P-channel transistor having a gate, a source and a drain;
• and
• a fourth N-channel transistor having a gate, a source and a drain coupled to said fourth P-channel transistor wherein the source of said fourth N-channel transistor is coupled to the drain of said fourth P-channel transistor and the drain of said fourth N-channel transistor is coupled to the source of said fourth P-channel transistor,
• wherein the source of said first P-channel transistor and the drain of said first N-channel transistor are coupled to a first supply voltage V.sub.dd,
• wherein the drain of said first P-channel transistor and the source of said first N-channel transistor are coupled to a second supply voltage V.sub.ss,
• wherein the gate of said first N-channel transistor is coupled to a first input signal V.sub.in.sup.+,
• wherein the gate of said first P-channel transistor is coupled to a second input signal V.sub.in .sup.-, wherein said second input signal V.sub.in.sup.- is approximately equal in magnitude and approximately opposite in phase from said first input signal V.sub.in.sup.-,
• wherein the source of said second P-channel transistor and the drain of said second N-channel transistor are coupled to a first supply voltage V.sub.dd via an impedance element,
• wherein the drain of said second P-channel transistor and the source of said second N-channel transistor are coupled to a second supply voltage V.sub.ss via an impedance element,
• wherein the gate of said second P-channel transistor is coupled to said first input signal V.sub.in.sup.+,
• wherein the gate of said second N-channel transistor is coupled to said second input signal V.sub.in.sup.-,
• wherein said third P-channel transistor and said third N-channel transistor are coupled between said first supply voltage V.sub.dd and said first P-channel transistor and said first N-channel transistor,
• wherein the gate of said third N-channel transistor is coupled to said first input signal V.sub.in.sup.+, wherein the gate of said third P-channel transistor is coupled to said second input signal V.sub.in.sup.-,
• wherein said fourth P-channel transistor and said fourth N-channel transistor are coupled between said first supply voltage V.sub.dd and said second P-channel transistor and said second N-channel transistor, and
• wherein the gate of said fourth P-channel transistor is coupled to said first input signal V.sub.in.sup.-, and wherein the gate of said fourth N-channel transistor is coupled to said second input signal V.sub.in.sup.-.