Using grooves as alignment marks when dicing an encapsulated semiconductor wafer
AssigneeOki Electric Industry Co., Ltd.
InventorShinji Ohuchi
Life of this patent
Estimating the term…
Abstract
Described herein is a method of manufacturing a semiconductor device according to the invention of the present application. According to the method, protruded electrodes are formed on a plurality of chip areas of a wafer having the plurality of chip areas on the surface thereof. Grooves are defined in boundary regions of the plurality of chip areas. Thereafter, the surface of the wafer with the grooves defined therein is covered with a resin. The back of the wafer is polished to expose the grooves from the back thereof. Next, the wafer is divided into pieces at the exposed groove portions. Since the grooves are bare from the back of the wafer in this way, the positions where the wafer is divided into the pieces, can be recognized with ease and reliability.
Claims17
A method of manufacturing a semiconductor device, comprising:
- forming electrodes on a plurality of chip areas of a wafer having said plurality of chip areas on an upper surface thereof and having a lower surface opposing said upper surface;
- forming grooves in boundary regions of said plurality of chip areas;
- covering said upper surface of said wafer with the grooves formed therein with a resin;
- polishing said lower surface so as to expose the grooves in the upper surface of the wafer from the back thereof;
- and
- dividing the wafer into pieces from the lower surface of the wafer using the grooves exposed from the lower surface of the wafer as marks, wherein the grooves are not exposed from the upper surface of the wafer.
A method of manufacturing a semiconductor device, comprising:
- forming plated wires with one end of each wire connected to one of a plurality of first electrodes, each plated wire being positioned on a protective film of a wafer containing a plurality of semiconductor elemental devices, each device being comprised of circuit elements, wherein the plurality of first electrodes are connected to said circuit elements and wherein the protective film for exposing the first electrodes and covering said circuit elements is formed over an upper surface of said wafer having an opposing bottom surface;
- forming a second electrode at each of the other ends of the plated wires;
- forming grooves between said plurality of semiconductor elemental devices on said upper surface;
- sealing said upper surface including said second electrodes with a resin;
- polishing said bottom surface to expose said grooves from the bottom surface;
- and
- cutting said wafer while viewing the bottom surface of the wafer by using the grooves exposed from the bottom surface of the wafer as guide marks, wherein the grooves are not exposed on the upper surface of the wafer.
Dependencies are inferred from the claim text.