CMOS semiconductor device comprising graded junctions with reduced junction capacitance

A method of manufacturing a semiconductor device, which method comprises:

• forming a dielectric layer on a surface of a semiconductor substrate;
• forming a conductive layer on the dielectric layer;
• patterning to form a gate electrode, having side surfaces, on the surface of the semiconductor substrate in an N-channel transistor region with a gate dielectric layer therebetween;
• using the gate electrode as a mask, ion implanting a first N-type impurity to form a lightly doped drain (N-LDD) implant:
• forming a first sidewall spacer, having a first width, on the side surfaces of the gate electrode;
• using the gate electrode and first sidewall spacer as a mask, ion implanting the first N-type impurity to form a moderately or heavily doped source/drain implant in the semiconductor substrate;
• forming a second sidewall spacer, having a second width, on the first sidewall spacer;
• using the gate electrode and the first and second sidewall spacers thereon as a mask, implanting a second N-type impurity, different from the first N-type impurity, to form a second N-type impurity implant in the semiconductor substrate;
• activation annealing to form:
• an N-LDD region, comprising the first N-type impurity, extending to a first depth below the surface of the semiconductor substrate;
• a moderately or heavily doped source/drain region, comprising the first N-type impurity, extending to a second depth greater than the first depth;
• and
• a region, comprising the second N-type impurity, extending to a third depth greater than the second depth and forming a graded junction extending under the source/drain region, thereby reducing junction capacitance.