Self-aligned methods of fabricating silicon carbide power devices by implantation and lateral diffusion

A method of fabricating a silicon carbide power device comprising the steps of:

• masking a surface of a silicon carbide substrate to define an opening at the surface;
• first implanting n-type dopants into the silicon carbide substrate through the opening at implantation energy and dosage that form a shallow n-type implant;
• electrically activating the n-type dopants;
• then implanting p-type dopants into the silicon carbide substrate through the opening at implantation energy and dosage that form a deep p-type implant relative to the shallow n-type implant;
• annealing at temperature and time that is sufficient to laterally diffuse the deep p-type implant to the surface of the silicon carbide substrate surrounding the shallow n-type implant, without vertically diffusing the deep p-type implant to the surface of the silicon carbide substrate through the shallow n-type implant;
• and
• implanting a p-type well at the surface of the silicon carbide substrate, electrically contacting the laterally diffused deep p-type implant.

A method of fabricating a silicon carbide lateral power MOSFET comprising the steps of:

• implanting an aluminum well into a drift region at a surface of a silicon carbide substrate;
• masking the drift region at the surface of the silicon carbide substrate to define a first pair of openings on the drift region, a respective one of which is on a respective opposite side of the aluminum well;
• first implanting p-type dopants into the silicon carbide substrate through the first pair of openings at implantation energy and dosage that form deep p-type implants;
• then implanting n-type dopants into the silicon carbide substrate through the first pair of openings at implantation energy and dosage that form shallow n-type implant relative to the deep p-type implants;
• masking the drift region at the surface of the silicon carbide substrate to define a second pair of openings on the drift region, a respective one of which is spaced apart from a respective shallow n-type implant and opposite the aluminum well;
• implanting n-type dopants into the silicon carbide substrate through the second pair of openings to define a pair of drain regions;
• annealing at temperature and time that is sufficient to laterally diffuse the respective deep p-type implants to the surface of the silicon carbide substrate surrounding the respective shallow n-type implants, without vertically diffusing the respective deep p-type implants to the surface of the silicon carbide substrate through the respective shallow n-type implants, to thereby form a pair of channel regions in the laterally diffused p-type implants at the surface of the silicon carbide substrate, a respective one of which is on a respective opposite side of the aluminum well;
• forming a pair of gate insulating regions on the drift region at the surface of the silicon carbide substrate, a respective one of which contacts a respective one of the pair of channel regions;
• and
• forming a common source contact, a pair of drain contacts and a pair of gate contacts on the shallow n-type implants and the aluminum well therebetween, on the drain regions, and on the pair of gate insulating regions, respectively.

A method of fabricating a silicon carbide lateral power MOSFET comprising the steps of:

• implanting an aluminum well into a drift region at a surface of a silicon carbide substrate;
• masking the drift region at the surface of the silicon carbide substrate to define a first pair of openings on the drift region, a respective one of which is on a respective opposite side of the aluminum well;
• first implanting n-type dopants into the silicon carbide substrate through the first pair of openings at implantation energy and dosage that form shallow n-type implants;
• electrically activating the n-type dopants;
• then implanting p-type dopants into the silicon carbide substrate through the first pair of openings at implantation energy and dosage that form deep p-type implants relative to the shallow n-type implants;
• masking the drift region at the surface of the silicon carbide substrate to define a second pair of openings on the drift region, a respective one of which is spaced apart from a respective shallow n-type implant and opposite the aluminum well;
• implanting n-type dopants into the silicon carbide substrate through the second pair of openings to define a pair of drain regions;
• annealing at temperature and time that is sufficient to laterally diffuse the respective deep p-type implants to the surface of the silicon carbide substrate surrounding the respective shallow n-type implants, without vertically diffusing the respective deep p-type implants to the surface of the silicon carbide substrate through the respective shallow n-type implants, to thereby form a pair of channel regions in the laterally diffused p-type implants at the surface of the silicon carbide substrate, a respective one of which is on a respective opposite side of the aluminum well;
• forming a pair of gate insulating regions on the drift region at the surface of the silicon carbide substrate, a respective one of which contacts a respective one of the pair of channel regions;
• and
• forming a common source contact, a pair of drain contacts and a pair of gate contacts on the shallow n-type implants and the aluminum well therebetween, on the drain regions, and on the pair of gate insulating regions, respectively.

A method of fabricating a silicon carbide vertical power MOSFET comprising the steps of:

• implanting a pair of spaced apart aluminum wells into a drift region at a surface of a silicon carbide substrate;
• masking the drift region at the surface of the silicon carbide substrate to define a first pair of openings on the drift region, between the pair of the aluminum wells;
• first implanting p-type dopants into the silicon carbide substrate through the first pair of openings at implantation energy and dosage that form deep p-type implants;
• then implanting n-type dopants into the silicon carbide substrate through the first pair of openings at implantation energy and dosage that form shallow n-type implants relative to the deep p-type implants;
• annealing at temperature and time that is sufficient to laterally diffuse the respective deep p-type implants to the surface of the silicon carbide substrate surrounding the respective shallow n-type implants, without vertically diffusing the respective deep p-type implants to the surface of the silicon carbide substrate through the respective shallow n-type implants, to thereby form a pair of channel regions in the laterally diffused p-type implants at the surface of the silicon carbide substrate, between the shallow n-type implants;
• forming a gate insulating region at the surface of the silicon carbide substrate extending on and between the pair of channel regions;
• forming a pair of source contacts, a gate contact and a drain contact on the respective shallow n-type implants and extending on the aluminum well adjacent thereto, on the gate insulating region, and on a second face of the silicon carbide substrate opposite the drift region, respectively.

A method of fabricating a silicon carbide vertical power MOSFET comprising the steps of:

• implanting a pair of spaced apart aluminum wells into a drift region at a surface of a silicon carbide substrate;
• masking the drift region at the surface of the silicon carbide substrate to define a first pair of openings on the drift region, between the pair of the aluminum wells;
• first implanting n-type dopants into the silicon carbide substrate through the first pair of openings at implantation energy and dosage that form shallow n-type implants;
• electrically activating the n-type dopants;
• then implanting p-type dopants into the silicon carbide substrate through the first pair of openings at implantation energy and dosage that form deep p-type implants relative to the shallow n-type implants;
• annealing at temperature and time that is sufficient to laterally diffuse the respective deep p-type implants to the surface of the silicon carbide substrate surrounding the respective shallow n-type implants, without vertically diffusing the respective deep p-type implants to the surface of the silicon carbide substrate through the respective shallow n-type implants, to thereby form a pair of channel regions in the laterally diffused p-type implants at the surface of the silicon carbide substrate, between the shallow n-type implants;
• forming a gate insulating region at the surface of the silicon carbide substrate extending one and between the pair of channel regions;
• forming a pair of source contacts, a gate contact and a drain contact on the respective shallow n-type implants and extending on the aluminum well adjacent thereto, on the gate insulating region, and on a second face of the silicon carbide substrate opposite the drift region, respectively.