Multithreaded processor for processing multiple instruction streams independently of each other by flexibly controlling throughput in each instruction stream

A multithreaded processor for executing multiple instruction streams, each of said multiple instruction streams may contain a special instruction to change a priority level of the corresponding instruction stream, the multithreaded processor comprising,

• a plurality of functional units for respectively executing instructions;
• a plurality of instruction decode means, corresponding to the multiple instruction streams on a one-to-one basis, for respectively decoding an instruction, and producing an instruction issue request for designating to which functional unit the decoded instruction should be issued and requesting for the issuance of the decoded instruction to the designated functional unit;
• priority holding means for holding the priority level of each instruction stream, wherein the priority level of each instruction stream is independent of the priority levels of the other instruction streams;
• self-halt data holding means for holding self-halt data indicating whether to put each instruction stream into an execution state or a halt state;
• arbitration means for determining, upon receipt of instruction issue request sent from the plurality of instruction decode means, which decoded instruction should be issued to the functional unit designated by two or more instruction issue request at the same time, in accordance with the priority levels held by the priority holding means;
• and
• stop means for stopping notification to the arbitration means of an instruction issue request from the instruction decode means corresponding to the instruction stream kept in a the halt state by the self hold data, the instruction issue request being one of the instruction issue request sent from the plurality of instruction decode means to the arbitration means;
• wherein one of the functional units receives the special instruction from one of the instruction streams for individually and independently changing the priority level of the corresponding instruction stream in the priority holding means.

A multithreaded processor for executing multiple instruction streams simultaneously and independently of each other, each of said multiple instruction streams may contain a special instruction to change a priority level of the corresponding instruction stream, the multithreaded processor comprising,

• a plurality of functional units for executing instructions simultaneously and independently of each other;
• a plurality of instruction decode means, corresponding to the multiple instruction streams on a one-to-one basis, for respectively fetching and decoding an instruction of each instruction stream, and specifying to which functional unit the instruction should be issued;
• priority designating means for designating the priority level of each of the multiple instruction streams, wherein each priority level is independent of the priority levels of the other instruction streams;
• instruction issue judging means for judging whether the decoded instruction can be issued to the specified functional unit, depending upon whether the specified functional unit is ready to receive an instruction;
• and
• instruction issue arbitration means for arbitrating between two or more instructions to determine one instruction to be issued to the functional unit specified by the two or more instruction decode means, in accordance with the priority levels designated by the priority designating means;
• wherein one of the functional units receives the special instruction from one of the instruction streams for individually and independently changing the priority level of the corresponding instruction stream designated by the priority designation means.

A multithreaded processor for executing multiple instruction streams simultaneously and independently of each other, each of said multiple instruction streams may contain a special instruction to change a priority level of the corresponding instruction stream, the multithreaded processor comprising,

• a plurality of functional units for executing instructions simultaneously and independently of each other;
• a plurality of instruction decode means, corresponding to the multiple instruction streams on a one-to-one basis, for respectively fetching and decoding an instruction of each instruction stream, and specifying to which functional unit the instruction should be issued;
• priority designating means for designating the priority level of each of the multiple instruction streams, and designating whether each instruction stream should be in an execution state or a in halt state, wherein each priority level is independent of the priority levels of the other instruction streams;
• instruction issue judging means for judging whether the decoded instruction can be issued to the specified functional unit, depending upon whether the specified functional unit is ready to receive an instruction;
• and
• instruction issue arbitration means for arbitrating between two or more instructions to determine one instruction to be issued to the functional unit specified by the two or more instruction decode means, in accordance with the priority levels designated by the priority designating means;
• wherein one of the functional units receives the special instruction from one of the instruction streams for individually and independently changing the priority level of the corresponding instruction stream designated by the priority designation means.

A multithreaded processor for executing multiple instruction streams simultaneously and independently of each other, each of said multiple instruction streams may contain a special instruction to change a priority level of the corresponding instruction stream, the multithreaded processor comprising,

• a plurality of instruction cache means for temporarily storing instructions of the multiple instruction streams;
• a plurality of instruction fetch means, corresponding to the multiple instruction streams on a one-to-one basis, for respectively fetching an instruction of each instruction stream from the instruction cache means;
• priority designating means for designating the priority level of each of the multiple instruction streams, wherein the priority level of each instruction stream is independent of the priority levels of the other instruction streams;
• and
• instruction fetch control means for arbitrating between instruction fetch request issued by two or more instruction cache means, in accordance with the priority levels designated by the priority designation means;
• wherein one of the functional units receives the special instruction from one of the instruction streams for individually and independently changing the priority level of the corresponding instruction stream designated by the priority designation means.

A multithreaded processor for executing multiple instruction streams, each of said multiple instruction streams may contain a special instruction to change a priority level of the corresponding instruction stream, the multithreaded processor provided with a plurality of functional units for executing instructions, a plurality of instruction decode means for respectively decoding an instruction fetched from an instruction cache means and outputting an instruction issue request to a designated functional unit, and the same number of register sets as the instruction decode means, which executes the same number of instruction streams as the instruction decode means simultaneously and independently of each other, the multithreaded processor comprising:

• holding means for holding the priority levels of each instruction stream that can be set by an instruction in each instruction stream, wherein the priority level of each instruction stream is independent of the priority levels of the other instruction streams;
• and
• control means for arbitrating between two or more instruction streams sharing the same resource, in accordance with the priority levels,
• the shared resource being one functional unit for which instruction issue request from two or more instruction decode means compete, one instruction cache for which fetch request from two or more instruction decode means compete, or one register set for which access request from two or more functional units competes;
• wherein one of the functional units receives the special instruction from one of the instruction streams for individually and independently changing the priority level of the corresponding instruction stream designated by the priority designation means.

A multithreaded processor for executing multiple instruction streams, each of said multiple instruction streams may contain a special instruction to change a priority level of the corresponding instruction stream, the multithreaded processor comprising:

• a plurality of functional units for respectfully executing instructions;
• a plurality of instruction decode means, corresponding to the multiple instruction streams on a one-to-one basis, wherein each instruction decode means decodes an instruction, produces an instruction issue request for designating to which functional unit the decoded instruction should be issued, and request an issuance of the decoded instruction to the designated functional unit;
• holding means for holding the priority level of each of the instruction streams, wherein each priority level is independent of the priority levels of the other instruction streams;
• control means for deciding which decoded instruction should be issued to a functional unit simultaneously designated by at least two instruction issue request, in accordance with the priority levels stored by the holding means;
• and
• changing means for individually and independently changing the priority level of an instruction stream held by the holding means according to the special instruction in the instruction stream to change the priority level.