US 6,105,119 A · Data transfer circuitry, DSP wrapper circuitry and improved processor devices, methods and systems

Abstract

An integrated circuit (1720) includes a dual-port memory (3330.1) having a first memory port (Port A) and a second memory port (Port B), a bus interface block (5010) including bus master (5016) and bus slave circuitry (5018), and a byte-channeling block (5310) coupled between the first memory port (Port A) and the bus interface block (5010) operable to convert non-aligned data addresses into aligned data. Advantageously, this invention includes a single bus master serving all application hardware. This relieves the host of the extra burden of communicating to slave circuits, reducing host I/O MIPS significantly. The digital signal processor with an ASIC wrapper of this invention together provide super-bus-mastering to access the entire memory space in the system, including the entire virtual memory space accessible by the host processor. Other processes, systems, devices and methods are also disclosed.

Claims2

Dependent claims

An integrated circuit comprising:

a dual-port memory having a first memory port and a second memory port;
a bus interface block including bus master and bus slave circuitry;
a byte-channeling block coupled between said first memory port and said bus interface block operable to convert non-aligned data into aligned data, said byte-channeling block determining a shift amount from a source memory address and a destination memory address, said byte-channeling block generating byte strobes selectively enabling writing into said dual-port memory in predetermined sets corresponding to said determined shift amount.

Dependencies are inferred from the claim text.

Data transfer circuitry, DSP wrapper circuitry and improved processor devices, methods and systems

Life of this patent

Data transfer circuitry, DSP wrapper circuitry and improved processor devices, methods and systems

Life of this patent

Abstract

Claims2