Computer system, memory device and shift register including a balanced switching circuit with series connected transfer gates which are selectively clocked for fast switching times

A balanced switching circuit, comprising:

• a first signal terminal adapted to receive an input signal;
• a first switch circuit having an input terminal coupled to the first signal terminal, an output terminal, and complementary control terminals adapted to receive first complementary control signals, the first switch circuit operable to couple its input terminal to its output terminal in response to the first complementary control signals;
• a second switch circuit having an input terminal coupled to the output terminal of the first switch circuit, an output terminal, and complementary control terminals adapted to receive second complementary control signals, the second switch circuit operable to couple its input terminal to its output terminal in response to the second complementary control signals;
• a third switch circuit having an input terminal coupled to the first signal terminal, an output terminal, and complementary control terminals coupled to the complementary control terminals of the second switch circuit and adapted to receive the second complementary control signals, the third switch circuit operable to couple its input terminal to its output terminal in response to the second complementary control signals;
• a fourth switch circuit having an input terminal coupled to the output terminal of the third switch circuit, an output terminal, and complementary control terminals coupled to the complementary control terminals of the first switch circuit and adapted to receive the first complementary control signals, the fourth switch circuit operable to couple its input terminal to its output terminal in response to the first complementary control signals;
• and
• a second signal terminal coupled to the output terminals of the second and fourth switch circuits, the balanced switching circuit operable to couple the first signal terminal to the second signal terminal in response to the first and second complementary control signals.

A shift register circuit, comprising:

• a transfer gate circuit having an input coupled to an input terminal, an output, and a clock terminal adapted to receive a clock signal, the transfer gate coupling its input to its output responsive to the clock signal;
• a first latch circuit having an output, and an input coupled to the output of the transfer gate, the first latch circuit storing a signal applied on its input and providing the stored signal on its output;
• a balanced switching circuit including a plurality of switch circuits, each switch circuit having an input terminal, an output terminal, and at least one control terminal adapted to receive a control signal, and operable to couple its input terminal to its output terminal in response to the control signal, the plurality of switch circuits arranged in N rows and N columns with the input and output terminals of the N switch circuits in each row connected in series between a first signal terminal and a second signal terminal, each switch circuit having its control terminal connected to one of N clock terminals adapted to receive respective clock signals, and each clock terminal coupled to the control terminal of only one switch circuit in each row and one switch circuit in each column, the balanced switching circuit operable to couple the first signal terminal to the second signal terminal in response to the clock signals;
• and
• a second latch circuit having an input coupled to the second signal terminal of the balanced switching circuit, the second latch circuit storing a signal applied on its input and providing the stored signal on its output.

A memory device, comprising:

• an address bus;
• a control bus;
• a data bus;
• an address decoder coupled to the address bus;
• a read/write circuit coupled to the data bus;
• a memory-cell array coupled to the address decoder, control circuit, and read/write circuit;
• and
• a control circuit coupled to the control bus and operable to control operation of the address decoder, read/write circuit, and memory-cell array in response to an external clock signal, the control circuit including a shift register circuit including a balanced switching circuit having a plurality of switch circuits, each switch circuit having an input terminal, an output terminal, and at least one control terminal adapted to receive a control signal, and operable to couple the input terminal to the output terminal in response to the control signal, the plurality of switch circuits arranged in N rows and N columns with the input and output terminals of the N switch circuits in each row connected in series between a first signal terminal and a second signal terminal, and each switch circuit having its control terminal connected to one of N clock terminals adapted to receive respective clock signals, and each clock terminal coupled to the control terminal of only one switch circuit in each row and one switch circuit in each column, the balanced switching circuit operable to couple the first signal terminal to the second signal terminal in response to the clock signals.