Network for packet-oriented data traffic

A node for a packet-oriented data traffic network comprising:

• high-speed interfaces coupled to communication lines of the packet-oriented data traffic network;
• a buffer circuit for reading a routing information in a head of a data packet, said buffer circuit being provided between said high-speed interfaces;
• at least one user interface with a wait line circuit;
• and
• a controller for processing data packets in transit, insert or output modes,
• a data packet remaining in said buffer circuit during the transit mode for a delay time that corresponds to a read cycle of said controller for reading routing information from the packet.

A network for packet-oriented data traffic, wherein several nodes are connected by communication lines to form a ring network, each node comprising:

• a least one user interface with a wait line for data packets which are inserted into or extracted from the ring network;
• high speed interfaces establishing connections between the communication lines of the ring network and the node, said high speed interfaces having a higher processing speed than said at least one user interface;
• a controller for processing data packets in transit, insert and extract modes;
• and
• a buffer circuit, coupled between said high speed interfaces, for enabling said controller to read a routing information in a head of a data packet, said buffer circuit operating at such a rate that delay time of the data packets in the transit mode is fixed and at least as long as a read cycle of said controller for reading the routing information.

A network for packet-oriented data traffic, wherein several nodes are connected by communication lines to form a ring network, each node comprising:

• a least one user interface with a wait line for data packets which are inserted into or extracted from the ring network;
• high speed interfaces establishing connections between the communication lines of the ring network and the node, said high speed interfaces having a higher processing speed than said at least one user interface;
• a controller for processing data packets in transit, insert and extract modes;
• and
• a buffer circuit, coupled between said high speed interfaces, for enabling said controller to read a routing information in a head of a data packet, a data packet being delayed in said buffer circuit during the transit mode for a delay time that is at least as long as a read cycle of said controller for reading the routing information and shorter than a time needed for inserting or extracting a data packet at a node during the insert and extract modes.