US 6,101,420 A · Method and apparatus for disambiguating change-to-dirty commands in a switch based multi-processing system with coarse directories

Abstract

An architecture and coherency protocol for use in a large SMP computer system includes a hierarchical switch structure which allows for a number of multi-processor nodes to be coupled to the switch to operate at an optimum performance. Within each multi-processor node, a simultaneous buffering system is provided that allows all of the processors of the multi-processor node to operate at peak performance. A memory is shared among the nodes, with a portion of the memory resident at each of the multi-processor nodes. Each of the multi-processor nodes includes a number of elements for maintaining memory coherency, including a victim cache, a directory and a transaction tracking table. The victim cache allows for selective updates of victim data destined for memory stored at a remote multi-processing node, thereby improving the overall performance of memory. Memory performance is additionally improved by including, at each memory, a delayed write buffer which is used in conjunction with the directory to identify victims that are to be written to memory. An arb bus coupled to the output of the directory of each node provides a central ordering point for all messages that are transferred through the SMP. The messages comprise a number of transactions, and each transaction is assigned to a number of different virtual channels, depending upon the processing stage of the message. The use of virtual channels thus helps to maintain data coherency by providing a straightforward method for maintaining system order. Using the virtual channels and the directory structure, cache coherency problems that would previously result in deadlock may be avoided.

Claims21

Dependent claims

A multi-processor computer system having a plurality of nodes coupled via a switch, each of the multi-processing nodes further comprising at least two processors, the multi-processor computer system comprising:

a shared memory apportioned into a plurality of blocks, each one of the plurality of nodes for storing a portion of the shared memory;
a directory, at each one of the plurality of nodes, coupled to the portion of shared memory of the node, for storing status information for each of the plurality of blocks in the portion of the shared memory of the associated node, the status information for indicating which of the plurality of nodes stores a copy of the associated block of shared memory;
a bus, at each one of the plurality of nodes, for coupling the at least two processors to the directory, the bus for carrying information including memory reference commands including an ownership command for gaining ownership of one of the blocks of the shared memory;
table, at each of the plurality of nodes, to track a status of the memory reference commands as to allow multiple memory reference commands to be in transit at a given time;
and
means, at each of the plurality of nodes, for inhibiting the transmission of an ownership command, issued by one of the least two processors of the respective node, requesting access to a given block of the shared memory in another one of the plurality of nodes by monitoring the table.

3 more elements

A method for maintaining order between a plurality of requests issued to a common address in a multi-processor computer system, the multi-processor computer system comprising a plurality of multi-processor nodes coupled via a switch, each of the multi-processor nodes comprising at least two processors and a portion of a s shared memory, the method comprising the steps of:

coupling a directory, at each one of the plurality of nodes, to the portion of shared memory of the node, to store status information for each of a plurality of blocks in the portion of the shared memory of the associated node, the status information for indicating which of the plurality of nodes stores a copy of the associated block of shared memory;
issuing, by the at least two processors, memory reference command including an ownership command for gaining ownership of one of the blocks of the shared memory;
coupling a table, at each of the plurality of nodes, to track a status of the memory reference commands as to allow multiple memory reference commands to be in transit at a given time;
and
inhibiting, at each one of the plurality of nodes, the transmission of an ownership command requesting access to a given block of the portion of shared memory in another one of the plurality nodes by monitoring the table.

2 more elements

Dependencies are inferred from the claim text.

Method and apparatus for disambiguating change-to-dirty commands in a switch based multi-processing system with coarse directories

Life of this patent

Method and apparatus for disambiguating change-to-dirty commands in a switch based multi-processing system with coarse directories

Life of this patent

Abstract

Claims21