US 6,101,197 A · Method and apparatus for adjusting the timing of signals over fine and coarse ranges

Abstract

A variable delay circuit is formed by a fine delay circuit and a coarse delay circuit. The fine delay circuit adjusts the delay of a delayed clock signal in relatively small phase increments with respect to an input clock signal. The coarse delay circuit adjusts the timing of a digital signal in relatively large phase increments. The delayed clock signal is used to clock a register to which the digital signal is applied to control the timing a the digital signal clocked through the register responsive to adjusting the timing of the fine delay circuit and the coarse delay circuit. The timing relationship is initially adjusted by altering the delay of the fine delay circuit. Whenever the maximum or minimum delay of the fine delay circuit is reached, the coarse delay circuit is adjusted. The variable delay circuit may be used in a memory device to control the timing at which read data is applied to the data bus of the memory device. The fine delay circuit includes a multi--tapped delay line coupled to a multiplexer that selects one of the taps for use in generating the delayed clock. When the first or last tap is selected, the timing of the coarse delay circuit is adjusted. The coarse delay circuit includes a counter that generates the digital signal upon counting from an initial count to the terminal count. The coarse delay circuit is adjusted by adjusting the initial count of the counter.

Claims54

Dependent claims

A variable delay circuit generating an output signal having a controlled timing, the variable delay circuit comprising:

a fine delay circuit receiving a clock signal and generating a delayed clock signal, the delayed clock signal having a delay relative to the clock signal that corresponds to a fine delay control signal applied to a control input of the fine delay circuit, the delay corresponding to the fine delay control signal being greater than a predetermined minimum delay and less than a predetermined maximum delay;
a coarse delay circuit controlling the timing of a digital signal relative to the clock signal in delay increments responsive to a coarse delay control signal applied to a control input of the coarse delay circuit;
and
a control circuit receiving a signal indicative of the delay of the fine delay circuit, the control circuit generating the coarse delay control signal to change the timing of the digital signal in one direction responsive to the delay of the fine delay circuit being within a predetermined range of the predetermined minimum delay, the control circuit generating the coarse delay control signal to change the timing of the digital signal in the opposite direction responsive to the delay of the fine delay circuit being within a predetermined range of the predetermined maximum delay;
and
a combining circuit for combining the delayed clock signal with the digital signal to provide the output signal having a timing corresponding to the combined delay of the fine delay circuit and the coarse delay circuit.

3 more elements

A command generator for memory device, the command generator outputting a control signal for the memory device to cause the memory device to output read data from a memory array responsive to an enable signal synchronized to a clock signal, the command generator comprising:

a fine delay circuit receiving the clock signal, the fine delay circuit generating a delayed clock signal having a delay relative to the clock signal corresponding to a fine delay control signal applied to a control input of the fine delay circuit, the delay corresponding to the fine delay control signal being greater than a predetermined minimum delay and less than a predetermined maximum delay;
a first control circuit generating the fine delay control signal as a function of a timing command;
a preloadable counter generating the control signal responsive to reaching a predetermined count, the counter being enabled to count toward the predetermined count responsive to the clock signal;
and
an up/down counter coupled to the preloadable counter, the up/down counter generating a preload count and loading the preload count into the preloadable counter prior to the counter being enabled by the clock signal, the up/down counter being incremented responsive an increment signal and being decremented responsive to a decrement signal;
and
a second control circuit generating the increment signal responsive to the delay of the fine delay circuit reaching one of the predetermined maximum or minimum delays, the second control circuit generating the decrement signal responsive to the delay of the fine delay circuit reaching the other of the predetermined maximum or minimum delays;
and
a read data register having a data input terminal coupled to the memory array to receive read data from the memory array, a data output terminal coupled to an externally accessible data bus terminal of the memory device, and a clock input receiving the delayed clock signal from the fine delay circuit, the read data register coupling data from the data input terminal to the data output terminal of the read data register responsive to the delayed clock signal.

6 more elements

A memory device, comprising:

a clock generator circuit receiving an external clock signal applied to a first externally accessible terminal and generating an internal clock signal having a phase shift relative to the external clock signal corresponding to a phase command signal applied to a control input of the clock generator circuit, the phase shift corresponding to the phase command signal being greater than a predetermined minimum phase and less than a predetermined maximum phase;
at least one array of memory cells adapted to store write data to and output read data from a location determined by a row address and a column address applied to respective other of the terminals;
a row address circuit adapted to receive and decode the row address, and select a row of memory cells corresponding to the row address;
a column address circuit adapted to receive read data from or apply write data to one of the memory cells in the selected row corresponding to the column address;
a command buffer receiving externally generated memory commands, the command buffer generating control signals responsive to the memory commands to control an operation of the memory device;
a data path circuit adapted to couple data between an externally accessible terminal of the memory device and the column address circuit, the data path circuit including a read register adapted to receive read data from the column address circuit and couple the read data to a data bus terminal responsive to the internal clock signal applied to a clock input of the read register;
a first control circuit generating the phase command signal as a function of a timing command signal;
and
a timer circuit controlling the timing of the read data being applied to the read register in fixed delay increments responsive to a signal indicative of the phase shift of the clock generator circuit, the timer circuit changing the timing of the read data applied to the read register in one direction responsive to the phase shift of the clock generator circuit being within a predetermined range of the predetermined minimum phase and in an opposite direction responsive to the phase shift of the clock generator circuit being within a predetermined range of the predetermined maximum phase.

6 more elements

A memory device, comprising:

at least one array of memory cells adapted to store data at a location determined by a row address and a column address applied to respective other of the terminals;
a row address circuit adapted to receive and decode the row address, and select a row of memory cells corresponding to the row address;
a column address circuit adapted to receive or apply data to one of the memory cells in the selected row corresponding to the column address;
a data path circuit including a write data register adapted to couple data from an externally accessible data bus terminal to the column address circuit, the data path circuit further including a read data register adapted to couple from the column address circuit to the externally accessible data bus terminal responsive to a read data clock signal;
a shift register receiving a plurality of command bits responsive to a clock signal derived from an external clock signal;
a timing control signal generating a count start signal responsive to a flag signal and a clock signal derived from an external clock signal applied to an externally accessible clock terminal;
a preloadable command counter causing data to be read from the memory array and applied to the read data register responsive to reaching a predetermined count, the counter being enabled to count toward the predetermined count responsive to the count start signal;
a clock generator circuit receiving the external clock signal and generating the read data clock signal having a phase shift relative to the external clock signal corresponding to a phase command signal applied to a control input of the clock generator circuit, the phase shift corresponding to the phase command signal being greater than a predetermined minimum phase and less than a predetermined maximum phase;
a first control circuit generating the phase command signal as a function of the phase relationship between the read data clock signal and the read data applied to the read data register;
an up/down counter coupled to the preloadable counter, the up/down counter generating a preload count and loading the preload count into the preloadable counter prior to the counter being enabled by the count start signal, the up/down counter being incremented responsive to the phase shift of the clock generator circuit reaching one of the predetermined maximum or minimum phases and being decremented responsive to the phase shift of the clock generator circuit reaching the other of the predetermined maximum or minimum phases.

7 more elements

A computer system, comprising:

a processor having a processor bus;
an input device coupled to the processor through the processor bus adapted to allow data to be entered into the computer system;
an output device coupled to the processor through the processor bus adapted to allow data to be output from the computer system;
and
a dynamic random access memory coupled to the processor bus adapted to allow data to be stored, adapted to receive a plurality of input signals and generate a plurality of output signals on respective, externally accessible terminals, the dynamic random access memory comprising:
a clock generator circuit receiving an external clock signal applied to a first externally accessible terminal and generating an internal clock signal having a phase shift relative to the external clock signal corresponding to a phase command signal applied to a control input of the clock generator circuit, the phase shift corresponding to the phase command signal being greater than a predetermined minimum phase and less than a predetermined maximum phase;
at least one array of memory cells adapted to store write data to and output read data from a location determined by a row address and a column address applied to respective other of the terminals;
a row address circuit adapted to receive and decode the row address, and select a row of memory cells corresponding to the row address;
a column address circuit adapted to receive read data from or apply write data to one of the memory cells in the selected row corresponding to the column address;
a command buffer receiving externally generated memory commands, the command buffer generating control signals responsive to the memory commands to control an operation of the memory device;
a data path circuit adapted to couple data between an externally accessible terminal of the memory device and the column address circuit, the data path circuit including a read register adapted to receive read data from the column address circuit and couple the read data to a data bus terminal responsive to the internal clock signal applied to a clock input of the read register;
a first control circuit generating the phase command signal as a function of a timing command signal;
and
a timer circuit controlling the timing of the read data being applied to the read register in fixed delay increments responsive to a signal indicative of the phase shift of the clock generator circuit, the timer circuit changing the timing of the read data applied to the read register in one direction responsive to the phase shift of the clock generator circuit being within a predetermined range of the predetermined minimum phase and in an opposite direction responsive to the phase shift of the clock generator circuit being within a predetermined range of the predetermined maximum phase.

11 more elements

A computer system, comprising:

a processor having a processor bus;
an input device coupled to the processor through the processor bus adapted to allow data to be entered into the computer system;
an output device coupled to the processor through the processor bus adapted to allow data to be output from the computer system;
and
a dynamic random access memory coupled to the processor bus adapted to allow data to be stored, adapted to receive a plurality of input signals and generate a plurality of output signals on respective, externally accessible terminals, the dynamic random access memory comprising:
at least one array of memory cells adapted to store data at a location determined by a row address and a column address applied to respective other of the terminals;
a row address circuit adapted to receive and decode the row address, and select a row of memory cells corresponding to the row address;
a column address circuit adapted to receive or apply data to one of the memory cells in the selected row corresponding to the column address;
a data path circuit including a write data register adapted to couple data from an externally accessible data bus terminal to the column address circuit, the data path circuit further including a read data register adapted to couple from the column address circuit to the externally accessible data bus terminal responsive to a read data clock signal;
a shift register receiving a plurality of command bits responsive to a clock signal derived from an external clock signal;
a timing control signal generating a count start signal responsive to a flag signal and a clock signal derived from an external clock signal applied to an externally accessible clock terminal;
a preloadable command counter causing data to be read from the memory array and applied to the read data register responsive to reaching a predetermined count, the counter being enabled to count toward the predetermined count responsive to the count start signal;
a clock generator circuit receiving the external clock signal and generating the read data clock signal having a phase shift relative to the external clock signal corresponding to a phase command signal applied to a control input of the clock generator circuit, the phase shift corresponding to the phase command signal being greater than a predetermined minimum phase and less than a predetermined maximum phase;
a first control circuit generating the phase command signal as a function of the phase relationship between the read data clock signal and the read data applied to the read data register;
an up/down counter coupled to the preloadable counter, the up/down counter generating a preload count and loading the preload count into the preloadable counter prior to the counter being enabled by the count start signal, the up/down counter being incremented responsive to the phase shift of the clock generator circuit reaching one of the predetermined maximum or minimum phases and being decremented responsive to the phase shift of the clock generator circuit reaching the other of the predetermined maximum or minimum phases.

12 more elements

A method of generating a delayed clock signal having a controlled timing relative to a digital signal, the method comprising:

generating the delayed clock signal responsive to an input clock signal, the delayed clock signal having a delay relative to the input clock signal that is adjustable over a relatively narrow range between a minimum delay value and a maximum delay value;
adjusting the timing of the delayed clock signal relative to the input clock signal;
generating the digital signal responsive to the input clock signal, the timing of the digital signal relative to the input clock signal being adjusted over a relatively broad range;
adjusting the timing of the digital signal relative to the input clock signal in one direction responsive to the delay of the delayed clock signal relative to the input clock signal approaching the minimum delay value;
and
adjusting the timing of the digital signal relative to the input clock signal in an opposite direction responsive to the delay of the delayed clock signal relative to the input clock signal approaching the maximum delay value.

3 more elements

A method of controlling the operation of a memory device applying read data to a read data register, and controlling a timing that the read data register is enabled to couple the read data through the read data register, comprising:

enabling the read data register responsive to a clock signal, the read data register being enabled at a time relative to the clock signal that is delayed over a relatively narrow range of delay values between a minimum delay value and a maximum delay value;
adjusting the delay value within the range of narrow range of delay values as a function of a timing of the read data being applied to the read data register relative to the timing that the read data register is enabled;
adjusting the timing that the read data is applied to the read data register relative to a timing of the clock signal in one direction responsive to the delay value approaching the minimum delay value;
and
adjusting the timing that the read data is applied to the read data register relative to the timing of the clock signal in an opposite direction responsive to the delay value approaching the maximum delay value.

2 more elements

Dependencies are inferred from the claim text.

Method and apparatus for adjusting the timing of signals over fine and coarse ranges

Life of this patent

Method and apparatus for adjusting the timing of signals over fine and coarse ranges

Life of this patent

Abstract

Claims54