Segmented dual delay-locked loop for precise variable-phase clock generation

A variable-phase clock generator comprising:

• an input clock having an input-clock period;
• a coarse-phase clock generator, receiving the input clock, the coarse-phase clock generator having a series of delay buffers, a phase detector, and a feedback, the feedback adjusting a total delay through the series of delay buffers to match the input-clock period in response to a phase difference detected by the phase detector;
• wherein the phase detector receives an input from the series of delay buffers within the coarse-phase clock generator, wherein the phase detector does not receive an input from the fine-phase clock generator, the phase detector matching a coarse delay but not matching a fine delay;
• wherein a plurality of intermediate clocks are output by the series of delay buffers in the coarse-phase clock generator, the plurality of intermediate clocks being offset in phase from each other;
• an intermediate selector, receiving the plurality of intermediate clocks, for selecting a selected intermediate clock from the plurality of intermediate clocks in response to a coarse phase-selector address;
• a fine-phase clock generator, receiving the selected intermediate clock from the intermediate selector, for generating a plurality of fine clocks, the plurality of fine clocks being offset in phase from each other by a smaller offset than the offset for the intermediate clocks;
• and
• an output selector, receiving the plurality of fine clocks, for selecting a selected fine clock from the plurality of fine clocks in response to a fine phase-selector address,
• whereby the selected fine clock has a phase offset between two adjacent intermediate clocks.

A segmented dual delay-locked-loop (DLL) clock generator comprising:

• an input clock;
• coarse DLL means, receiving the input clock, for generating a plurality of intermediate clocks each having a different phase but having a same period as the input clock, the coarse DLL means having feedback loop means for adjusting phase offsets of the intermediate clocks;
• intermediate mux means, receiving the plurality of intermediate clocks, for outputting a K clock and a K+1 clock, wherein the K+1 clock has a phase immediately following a phase of the K clock;
• a fine DLL means, receiving the K clock and the K+1 clock from the intermediate mux means, for generating a plurality of fine clocks each having a different phase between the phase of the K clock and the phase of the K+1 clock, wherein the plurality of fine clocks all have the same period as the input clock;
• and
• output mux means, receiving the plurality of fine clocks from the fine DLL means, for outputting a generated clock
• whereby the intermediate mux means selects a coarse phase from the plurality of clocks generated by the coarse DLL means, while the output mux means selects a fine phase between phases of two adjacent intermediate clocks from the intermediate mux means.