Clock latency compensation circuit for DDR timing

#It is important that data output transitions associated with an integrated circuit, e.g., a memory (dynamic random access memory (DRAM) or static random access memory (SRAM)), or other timing critical device occur in synchronized fashion with a system clock to the integrated circuit. Lack of data output synchronization with the system clock is often described in terms of clock to data latency.

#Latency problems have been addressed in the past through use of a delay locked loop (DLL) which is illustrated in the schematic drawing of FIG. 1. In a DLL, phase comparator 2 controls delay line 4 so that the phase difference between clock signals Ckin and Ckout is zero. The time delay provided by delay line 4 stabilizes when the delay between signals Ckin and Ckout is k*T, where T is the period of clock signal Ckin and k is a natural number. Prior art schemes to eliminate clock to data latency generally work with reference to the rising edge of a clock. Latency problems with respect to the falling edge of a clock are not addressed. Consequently, such schemes are not well suited for double data rate applications such as those concerning double data rate synchronous dynamic random access memories (DDR SDRAMs). A need exists to compensate for clock to data latency pertaining to double data rate applications.

#FIG. 1 is a schematic drawing of conventional delay locked loop (DLL).

#FIG. 2 illustrates a schematic drawing of a preferred embodiment of the invention.

#FIG. 3 illustrates a timing diagram showing the operation of the circuit in FIG. 2.

#Reference numerals and symbols have been carried forward.

#The invention solves the double data rate clock to data latency problem through the implementation of two clocks: one triggered by the rising edge of the system clock and the other triggered by the falling edge of the system clock. The said two generated clocks are phase adjusted through two delay lines with common control.

#FIG. 2 illustrates a schematic drawing of preferred embodiment of a circuit according to the invention which can be fabricated on an integrated circuit. The circuit in FIG. 2 allows synchronization of data output from an integrated circuit with the rising and falling edges of a system clock input to the integrated circuit. Such a circuit can be ideally used in conjunction with double data rate applications. Receiver 6 receives the system clock signal CLK and produces two clock signals, CLK1 and CLK2 respectively, which are input to the respective delay lines 4 and 5, delay line 4 forms a delay-locked loop (DLL) with phase comparator 2. Delay line 4 can be constructed of active or passive variable impedance circuitry or it can be derived from microcomputer, microcontroller, or digital signal processor. In its preferred embodiment, receiver 6 comprises two conventional monostable multivibrator circuits or one-shot circuits, one of which triggers off of the rising edge of the system clock and the other of which triggers off of the falling edge of the system clock. A monostable multivibrator circuit or one-shot circuit can be implemented as a flip-flop with one stable state. Delay R is the propagation delay associated with receiver 6. Delay D is the propagation delay associated with the driver circuitry 7 comprising driver 8 and OR gate 10. Delay element 12 provides compensation via a DLL loop (which includes a path through elements 2, 4, and 12) through introduction of phase delay .tau.=R+D in the loop. When the synchronization is reached, the delay of the output signal with respect to the input clock is k*T. So, the delay of the signal entering the driver circuitry 7 with respect to the input clock is k*T-D, where D is the propagation delay of the driver 7. Phase comparator 2 need not output phase compensation causing data to delay lines 4 and 5 when a comparison of the phase input by phase comparator 2 results in the information at input 14 of phase comparator 2 having a delay of k*T relatively to the information at input 16 of phase comparator 2. (R delay at input 16 and tau+k*T-D=R+D+k*T-D=R+k*T at input 14). Should this relationship not exist, phase comparator 2 causes delay lines 4 to increase or decrease the delay associated with delay line 4 via a control signal from output 18 of phase comparator 2 so as to achieve the above described R delay condition at inputs 14 and 16. The delay lines 4 and 5 output a respective time-shifted version of the clock signal at delay lines 4 and 5s input (e.g., CLK1' being a time-shifted version of CLK1 and CL2' being a time-shifted version of CLK2). Logic involving the ORing of clock signals CLK1' and CLK2' to produce an input to driver 8, which also receives an input from output data 9, yields data signal DQ.