Method of making a dual damascene interconnect structure using low dielectric constant material for an inter-level dielectric layer

A process for fabricating a dual damascene integrated circuit on a semiconductor substrate, said process comprising the steps of:

• forming with a co-planar upper surface a copper metal line in a dielectric layer;
• selectively depositing an etch-stop conductive barrier/encapsulation layer only on said upper surface of said copper metal line;
• depositing a first low-.di-elect cons. ILD dielectric layer over said conductive barrier/encapsulation layer and said dielectric layer;
• forming on said first low-.di-elect cons. ILD dielectric layer a first etch-stop dielectric layer having a defined via opening;
• depositing a second low-.di-elect cons. ILD dielectric layer over said first etch-stop layer;
• forming on said second low-.di-elect cons. ILD dielectric layer a second etch-stop dielectric layer having a defined trench opening;
• anisotropically etching said second low-.di-elect cons. ILD dielectric layer through said trench opening to said first etch stop dielectric layer, and thereafter anisotropically etching said first low-.di-elect cons. ILD dielectric layer through said via opening to said conductive barrier/encapsulation layer, creating a trench cavity in layer and a via cavity in layer;
• forming a conductive barrier layer on said second etch-stop dielectric layer and on the inner surfaces defined by said trench and said via cavities, said conductive barrier layer connecting to said conductive barrier/encapsulation layer;
• depositing continuous copper metal to fill the space defined within said conductive barrier layer;
• removing excess copper metal and conductive barrier layer material disposed on said second etch-stop dielectric layer, to form a planar surface consisting of an upper surface of said copper metal, horizontal wall tops of said conductive barrier layer and said second etch-stop layer;
• and
• selectively depositing an etch-stop conductive barrier/encapsulation layer on said upper surface of said copper metal and said horizontal wall tops of said barrier layer material, thus to fully encapsulate said copper metal.