US 6,097,768 A · Phase detector for carrier recovery in a DQPSK receiver

Abstract

A phase detector using simple arithmetic operations to measure phase errors in the carrier-recovery mechanism for a DQPSK digital communications receiver. The carrier-recovery mechanism is a feedback loop that provides a synchronization between the oscillators in the transmitter and receiver of the communications system; the phase detector measures deviations from this synchronization and generates a phase-error signal used in the feedback loop to synchronize the oscillators. To perform this measurement, the phase detector takes the received signal as input and compares it against a local oscillator in the receiver to generate two digital signals: the in-phase (I) and quadrature-phase (Q) components of the received signal. These signals are the input to a logic unit, which uses these two signals to determine the phase-error signal. In one embodiment of the phase detector, the logic unit analyzes the signs of the two digital signals and then accordingly adds or subtracts the I and Q signals to generate the phase-error signal. In another embodiment, the logic unit determines the magnitude of the phase-error signal by finding the difference in magnitudes of the two digital signals and constructing a phase-error signal proportional to this difference. The logic unit then determines the sign of the phase-error signal by analyzing the signs of the I and Q digital signals. The logic unit thus uses simple arithmetic operations to generate the phase-error signal, thereby reducing the complexity and cost of the phase detector.

Claims9

Dependent claims

A phase detector for detecting a phase difference between a transmitter oscillator and a receiver oscillator in a differential quadriphase-shift-keying communications system, the phase detector comprising:

a first mixer that receives a received signal, wherein said received signal includes a frequency and phase generated by said transmitter oscillator, and wherein said first mixer multiplies said received signal with an in-phase signal of said receiver oscillator, and wherein said first mixer generates a first mixer output;
a second mixer that receives said received signal, wherein said second mixer multiplies said received signal with a quadrature-phase signal of said receiver oscillator, and wherein said second mixer generates a second mixer output;
a first sampling unit coupled to receive said first mixer output, wherein said first sampling unit produces a first digital signal comprising a sign and a magnitude, and wherein said first digital signal represents an in-phase component of said received signal in response to said first mixer output;
a second sampling unit coupled to receive said second mixer output, wherein said second sampling unit produces a second digital signal comprising a sign and a magnitude, and wherein said second digital signal represents a quadrature-phase component of said received signal in response to said second mixer output;
and
a logic unit coupled to said first sampling unit and to said second sampling unit wherein said logic unit receives said first and second digital signals, wherein said logic unit operates to calculate a phase-error signal that represents said phase difference between said transmitter oscillator and said receiver oscillator, and wherein said logic unit detects the difference between the magnitudes of said first and second digital signals in calculating the phase error signal.

3 more elements

a first digital mixer that receives a received digital signal, wherein said received digital signal includes a frequency and phase generated by said transmitter oscillator, wherein said first digital mixer multiplies said received digital signal with an in-phase digital signal of said receiver oscillator, and wherein said first digital mixer generates a first digital mixer output;
a second digital mixer that receives said received digital signal, wherein said second digital mixer multiplies said received digital signal with a quadrature-phase digital signal of said receiver oscillator, and wherein said second digital mixer generates a second digital mixer output;
a first digital filter coupled to the first digital mixer, wherein said first digital filter filters said first digital mixer output to generate a first digital filter output;
a second digital filter coupled to the second digital mixer, wherein said second digital filter filters said second digital mixer output to generate a second digital filter output;
a first decimator coupled to the first digital filter that samples said first digital filter output to generate a first digital signal at a sample rate;
a second decimator coupled to the second digital filter that samples said second digital filter output to generate a second digital signal at a sample rate;
and
a logic unit coupled to said first decimator and to said second decimator wherein said logic unit receives said first and second digital signals, wherein said logic unit operates to calculate a phase-error signal that represents said phase difference between said transmitter oscillator and said receiver oscillator, and wherein said logic unit detects the difference between the magnitudes of said first and second digital signals.

5 more elements

a first digital sampler that receives a received signal, wherein said received signal includes a frequency and phase generated by said transmitter oscillator, wherein said first digital sampler samples said received signal at a sample rate, and wherein said first digital sampler generates a first digital sampler output;
a second digital sampler that receives an in-phase signal of said receiver oscillator, wherein said second digital sampler samples said in-phase signal at a sample rate, and wherein said second digital sampler generates an in-phase digital signal;
a third digital sampler that receives a quadrature-phase signal of said receiver oscillator, wherein said third digital sampler samples said quadrature-phase signal at a sample rate, and wherein said third digital sampler generates a quadrature-phase digital signal;
a first digital mixer that multiplies said first digital sampler output with said in-phase digital signal, and wherein said first digital mixer generates a first digital mixer output;
a second digital mixer that multiplies said first digital sampler output with said quadrature-phase digital signal, and wherein said second digital mixer generates a second digital mixer output;
a first digital filter coupled to the first digital mixer, wherein said first digital filter filters said first digital mixer output to generate a first digital filter output;
a second digital filter coupled to the second digital mixer, wherein said second digital filter filters said second digital mixer output to generate a second digital filter output;
a first decimator coupled to the first digital filter that samples said first digital filter output to generate a first digital signal at a sample rate;
a second decimator coupled to the second digital filter that samples said second digital filter output to generate a second digital signal at a sample rate;
and
a logic unit coupled to said first decimator and to said second decimator wherein said logic unit receives said first and second digital signals, wherein said logic unit operates to calculate a phase-error signal that represents said phase difference between said transmitter oscillator and said receiver oscillator, and wherein said logic unit detects the difference between the magnitudes of said first and second digital signals .

8 more elements

Dependencies are inferred from the claim text.

Phase detector for carrier recovery in a DQPSK receiver

Life of this patent

Phase detector for carrier recovery in a DQPSK receiver

Life of this patent

Abstract

Claims9