Power output stage for the control of plasma screen cells
AssigneeSTMicroelectronics S.r.l.
InventorsGilles Troussel, Celine Lardeau
Life of this patent
Estimating the term…
Abstract
The present invention relates to a power output stage for the control of plasma screen cells. It includes VDMOS-type N-channel charge and discharge transistors, the charge transistor being arranged to form a compound P-channel transistor. These transistors enable to issue a charge current to an output and to absorb a discharge current from this output. Two inverters are sized so that the potential of the control gate of the charge transistor drops more rapidly than the output potential when a discharge of this output is controlled. Thus, an output stage of limited bulk and without any risk of simultaneous conduction of the charge and discharge transistors is implemented.
Claims17
A power output stage for the control of plasma screen cells, comprising:
- an input for receiving a low voltage logic input signal, a control output for issuing a high voltage output control signal, and an output circuit including a charge transistor receiving a high voltage potential on a drain and having a source connected to the control output and a discharge transistor receiving a reference potential on a source and having a drain connected to the control output, and a control circuit issuing control signals to the charge and discharge transistors to control these transistors according to the logic input signal, wherein the charge and discharge transistors are of N-channel VDMOS type, the charge transistor being arranged to form a compound P-type transistor, and wherein the control circuit is arranged so that a potential of a control gate of the charge transistor drops more rapidly than the output potential when the logic input signal controls a discharge of the control output.
A power output circuit for converting a logic signal of a low voltage to an output signal of a high voltage, the power output circuit comprising:
- an input terminal coupled to receive the logic signal;
- an output terminal;
- a charge transistor of a first conductivity type having a first terminal coupled to a high voltage source, a second terminal coupled to the output terminal, and a control terminal;
- a discharge transistor of the first conductivity type having a first terminal coupled to the output terminal, a second terminal coupled to a low voltage source, and a control terminal;
- a control circuit for controlling a conductive state of the charge transistor and the discharge transistor, the control circuit having an input coupled to the input terminal, a first output coupled to the control terminal of the charge transistor, and a second output coupled to the control terminal of the discharge transistor, the control circuit being structured to render the charge transistor non-conductive before rendering the discharge transistor conductive and to render the discharge transistor non-conductive before rendering the charge transistor conductive based on the logic signal to alternately couple the output terminal to either the high voltage source or the low voltage source.
A method for converting a logic signal of a low voltage to an output signal at a high voltage, the method comprising:
- generating a plurality of delayed control signals based on the logic signal;
- rendering a high side transistor of a first conductivity type conductive with one of the control signals to couple a high voltage source to an output terminal;
- rendering the high side transistor non-conductive with one of the control signals;
- rendering a low side transistor of the first conductivity type conductive with one of the control signals to couple a low voltage source to the output terminal after the high side transistor has been rendered non-conductive;
- and
- rendering the low side transistor non-conductive with one of the control signals.
Dependencies are inferred from the claim text.