Method for forming pillar memory cells and device formed thereby

A method for forming buried bitlines to connect memory cells on a semiconductor substrate, the method comprising the steps of:

• a) forming a trench having sidewalls and a bottom in the substrate;
• b) conformally depositing a dopant source layer on the substrate, said dopant source layer covering the trench sidewalls and trench bottom;
• c) conformally forming a resist layer on the dopant source layer, said resist layer covering said dopant source layer on the trench sidewalls and trench bottom;
• d) exposing the resist layer at an angle by implanting into the resist layer such that upper portions of the resist layer on the trench sidewalls are exposed and lower portions of the resist layer on the trench sidewalls are blocked by the trench sidewalls and unexposed;
• e) removing the exposed portion of the resist layer and the dopant source layer beneath the exposed portion of the resist layer;
• f) diffusing dopant from the unexposed portion of the dopant source layer into the substrate to form a diffusion region;
• and
• g) further etching the bottom of the trench such that the diffusion region is divided into two source/drain/bitline diffusion regions.

A method for forming a buried plates in a memory cell on a semiconductor substrate, the method comprising the steps of:

• a) forming a trench having sidewalls and a bottom in the substrate;
• b) conformally depositing a dopant source layer on the substrate, said dopant source layer covering the trench sidewalls and trench bottom;
• c) conformally forming a resist layer on the dopant source layer, said resist layer covering said dopant source layer on the trench sidewalls and trench bottom;
• d) exposing the resist layer at an angle by implanting into the resist layer such that upper portions of the resist layer on the trench sidewalls are exposed and lower portions of the resist layer on the trench sidewalls are blocked by the trench sidewalls and unexposed;
• e) removing the exposed portion of the resist layer and the dopant source layer beneath the exposed portion of the resist layer;
• and
• f) diffusing dopant from the unexposed portion of the dopant source layer into the substrate to form a buried plate diffusion region.