MOS transistors having vertical current flow
AssigneesConsorzio per la Ricerca Sulle Microelettronica nel Mezzogiorno, STMicroelectronics S.r.l.
InventorsRaffaele Zambrano, Carmelo Magro
Life of this patent
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Abstract
The process provides first for the accomplishment of low-doping body regions at the sides and under a gate region and then the accomplishment of high-doping body regions inside said low-doping body regions and self-aligned with said gate region. There is thus obtained an MOS power transistor with vertical current flow which has high-doping body regions self-aligned with said gate region and with a reduced junction depth.
Claims23
A semiconductor transistor structure, comprising:
- an epitaxial semiconductor layer;
- a gate insulating layer overlying a portion of the epitaxial semiconductor layer;
- a gate conductor overlying the gate insulating layer;
- a lightly doped region of a first conductivity type within the epitaxial semiconductor layer and extending under the rate conductor;
- a heavily doped region of the first conductivity type within the epitaxial semiconductor layer and contained within the lightly doped region;
- and
- a source region of a second conductivity type within the epitaxial semiconductor layer adjacent to the gate conductor, wherein the heavily doped region is deeper under said source region than in all locations not under said source region.
A semiconductor transistor structure, comprising:
- a semiconductor substrate;
- an epitaxial semiconductor layer overlying the semiconductor substrate;
- a gate insulating layer overlying a portion of the epitaxial semiconductor layer;
- a gate conductor overlying the gate insulating layer;
- a lightly doped region of a first conductivity type on the epitaxial semiconductor layer and extending under the gate conductor;
- a heavily doped region of the first conductivity type in the lightly doped region;
- and
- a source region of a second conductivity type different than the first conductivity type in a portion of the heavily doped region and a portion of the lightly doped region, wherein said heavily doped region is deeper under said source region than in all locations not under said source region.
A power MOS transistor with vertical current flow, comprising:
- a silicon substrate having a high concentration of dopant of a first conductivity type;
- an epitaxial layer with a low concentration of dopant of the first conductivity type on the substrate;
- a gate oxide layer on a surface portion of the epitaxial layer;
- a polycrystalline silicon gate layer on the gate oxide layer;
- lightly doped regions with a dopant of a second conductivity type formed in the epitaxial layer adjacent to and partially below the surface portion of the epitaxial layer beneath the gate oxide layer;
- heavily doped regions with a dopant of the second conductivity type formed in the lightly doped body regions aligned with the gate layer;
- and
- source regions with a dopant of the first conductivity type formed in portions of the heavily doped body regions, wherein said heavily doped body regions are deeper under said source regions than in all locations not under said source regions.
Dependencies are inferred from the claim text.