Method of fabricating integrated circuits with oxidized isolation

The method of forming a plurality of electrically isolated pockets of semiconductor material in a semiconductor structure comprising a silicon substrate of one conductivity type with an epitaxial silicon layer thereon of said one conductivity type which comprises the steps of:

• forming directly beneath portions of the top surface of said substrate low resistivity regions of opposite conductivity type to said one conductivity type, such that a laterally-extending PN junction is formed between said low resistivity regions and said silicon substrate;
• growing a doped epitaxial silicon layer of said one conductivity type on said silicon substrate;
• forming a layer of insulation on the top surface of said epitaxial silicon layer, said insulation having the properties that it is substantially unaffected by at least one etchant used to remove epitaxial silicon and substantially masks the diffusion of oxygen;
• removing portions of said insulation overlying regions of said epitaxial silicon layer to be converted into oxidized silicon;
• forming depressions to a specified depth in said epitaxial silicon exposed by removal of said insulation by removing part of said epitaxial silicon exposed by removal of said insulation;
• subdividing said epitaxial silicon layer into a plurality of electrically isolated pockets of semiconductor material by oxidizing the silicon exposed by said depressions to form oxidized silicon, said depth being selected such that the oxidized silicon has an upper surface approximately coplanar with the top surface of the remaining portions of said epitaxial layer and has a bottom surface in contact with said laterally extending PN junction thereby to surround each pocket of semiconductor material by an annular-shaped region of oxidized silicon;
• removing said layer of insulation after the silicon exposed by said depressions is oxidized through to said laterally extending PN junction;
• introducing an impurity of said one conductivity type into a selected region of said epitaxial silicon surrounded by an annular-shaped region of oxidized silicon to form a more highly doped region of said one conductivity type;
• masking said epitaxial silicon layer to leave exposed the surface of another region of epitaxial silicon above one of said low resistivity regions in said silicon substrate, said another region of epitaxial silicon being surrounded by another annular-shaped region of oxidized silicon;
• and
• introducing an impurity of said opposite conductivity type into said another region of epitaxial silicon.

A fabrication method comprising the steps of:

• creating a structure in which a doped epitaxial silicon layer is grown on a doped silicon semiconductor substrate predominantly of one conductivity type, the epitaxial layer being predominantly of opposite conductivity type to said one conductivity type such that a PN isolation junction extends laterally along at least part of the interface between the substrate and the epitaxial layer, and in which a low resistivity buried layer of said opposite conductivity type is provided along the interface between the substrate and the epitaxial layer;
• forming an insulation layer over the epitaxial layer, the insulation layer being substantially impervious to the penetration of oxygen;
• removing selected material of the insulation layer down to the epitaxial layer to create a pattern of one or more openings through the insulation layer;
• removing epitaxial silicon exposed through each opening to form a pattern of one or more depressions extending partway through the epitaxial layer;
• and
• subdividing the epitaxial layer into a plurality of laterally separated pockets of semiconductor material by thermally oxidizing silicon exposed at each depression to form a patterned electrically insulating region of oxidized silicon extending at least partway through the epitaxial layer, the insulating region extending down to the PN isolation junction such that each pocket of semiconductor material is laterally surrounded by oxidized silicon and is electrically isolated from each other pocket by surrounding oxidized silicon and a part of the PN isolation junction, the insulating region and the isolated pockets having largely co-planar upper surfaces, the low resistivity layer having been provided at such a location that the low resistivity layer forms part of a selected one of the isolated pockets of semiconductor material, the selected pocket including first and second epitaxial silicon portions laterally separated by oxidized silicon, both epitaxial portions being contiguous with the low resistivity layer.

A fabrication method comprising the steps of:

• creating a structure in which a doped epitaxial silicon layer predominantly of one conductivity type is grown on a doped silicon substrate predominantly of said one conductivity type, laterally separated low resistivity buried layers of opposite conductivity type to said one conductivity type being provided in the structure along the interface between the substrate and the epitaxial layer so as to form a PN isolation junction between the substrate and the low resistivity layers;
• forming an insulation layer over the epitaxial layer, the insulation layer being substantially impervious to the penetration of oxygen;
• removing selected material of the insulation layer down to the epitaxial layer to create a pattern of one or more openings through the insulation layer;
• removing epitaxial silicon exposed through each opening to form a pattern of one or more depressions extending partway through the epitaxial layer;
• and
• subdividing the epitaxial layer into a plurality of laterally separated pockets of semiconductor material by thermally oxidizing silicon exposed at each depression to form a patterned electrically insulating region of oxidized silicon extending at least partway through the epitaxial layer, the insulating region extending down to the PN isolation junction such that each pocket of semiconductor material is laterally surrounded by oxidized silicon and is electrically isolated from each other pocket by surrounding oxidized silicon and a part of the PN isolation junction, the insulating region and the isolated pockets having largely co-planar upper surfaces, a selected one of the pockets including first and second epitaxial silicon portions laterally separated by oxidized silicon, both epitaxial portions being contiguous with a specified one of the low resistivity layers.