Flexible implementation of a system management mode (SMM) in a processor
AssigneeAdvanced Micro Devices, Inc.
InventorsJohn G. Favor, Frederick D. Weber
Life of this patent
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Abstract
A system management mode (SMM) of operating a processor includes only a basic set of hardwired hooks or mechanisms in the processor for supporting SMM. Most of SMM functionality, such as the processing actions performed when entering and exiting SMM, is "soft" and freely defined. A system management interrupt (SMI) pin is connected to the processor so that a signal on the SMI pin causes the processor to enter SMM mode. SMM is completely transparent to all other processor operating software. SMM handler code and data is stored in memory that is protected and hidden from normal software access.
Claims33
A network server comprising:
- a superscalar processor including an instruction decoder;
- an external memory coupled to the superscalar processor and operable to store a plurality of modifiable encoded SMM instructions defined by RISC operation sequences;
- a means coupled to the superscalar processor for activating a system management activation signal;
- an instruction memory coupled to the superscalar processor and operable to store a software program including:
- an SMM initialization routine defined by at least a first one of the plurality of modifiable encoded SMM instructions;
- a routine for redirecting SMM operations to the plurality of modifiable encoded SMM instructions;
- and
- an SMM termination routine defined by at least a second one of the plurality of modifiable encoded SMM instructions;
- a processor bus coupled between the instruction memory and the superscalar processor;
- a local bus and an I/O bus;
- first and second bridges, respectively coupling the processor bus to the local bus and the local bus to the I/O bus;
- and
- a LAN adapter coupled to one of the local bus and the I/O bus.
A multimedia computer system incorporating a processor including an adaptable system management mode (SMM) implementation, the multimedia computer system comprising:
- a multimedia performance device;
- a multimedia adapter coupled to the multimedia performance device and coupled to the multimedia signal acquisition device, the multimedia adapter including a signal conversion interface for synthesizing and sampling multimedia signals;
- an input/output bus coupled to the multimedia adapter for communicating transfers of multimedia data;
- a superscalar processor coupled to the input/output bus for processing multimedia data and controlling communication of multimedia data between the superscalar processor and the multimedia adapter, the superscalar processor including an instruction decoder;
- an external memory coupled to the superscalar processor and operable to store a plurality of modifiable encoded SMM instructions defined by RISC operation sequences;
- a means coupled to the superscalar processor for activating a system management activation signal;
- and
- an instruction memory coupled to the superscalar processor and operable to store a software program including:
- an SMM initialization routine defined by at least a first one of the plurality of modifiable encoded SMM instructions;
- a routine for redirecting SMM operations to the plurality of modifiable encoded SMM instructions;
- and
- an SMM termination routine defined by at least a second one of the plurality of modifiable encoded SMM instructions.
Dependencies are inferred from the claim text.