Method and apparatus for arbitrating between command streams
AssigneeIntel Corporation
InventorsDavid J. Harriman, Brian K. Langendorf, Jasmin Ajanovic
Life of this patent
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Abstract
A method and apparatus for arbitrating between command streams. The method unblocks high priority commands which are blocked and then selects any remaining high priority commands. Normal priority commands are selected after the high priority commands. A memory controller described includes a command queue block having a plurality of command queues, each being coupled to receive a different type of command. The memory controller also includes arbitration logic which, among other things, selects high priority read commands before high priority write commands. Memory interface logic generates memory accesses performing commands selected by the arbitration logic.
Claims19
A memory controller comprising:
- a command queue block having a plurality of command queues including a high priority queue, a normal priority read queue, and a normal priority write queue, each of said plurality of command queues being coupled to receive a different type of command with said high priority queue receiving both high priority read commands and high priority write commands;
- arbitration logic coupled to said command queue block to select an available high priority read before an available high priority write, wherein said available high priority write is selected after said available high priority read if said high priority write is an unblocked high priority write, and wherein said arbitration logic is coupled to unblock a blocked high priority write before selecting said available high priority read;
- and
- memory interface logic coupled to said arbitration logic to generate a memory access performing a selected command.
A system comprising:
- a main memory;
- a bus agent configured to generate a plurality of commands to access said main memory;
- a processor;
- and
- a memory controller coupled to said processor, said main memory, and coupled to receive said plurality of commands from said bus agent, said memory controller including
- a normal priority read queue;
- a normal priority write queue;
- a high priority read and write queue;
- said memory controller to unblock high priority write commands from said bus agent by elevating a priority level for all write commands in either the normal priority write queue or the high priority read and write queue prior to a blocked high priority write command, and to select an available high priority read command over an available high priority write command unless said available high priority write command is a blocked high priority write command.
A method of arbitrating between command streams, comprising:
- unblocking a blocked high priority command which is a high priority write command by
- elevating a priority level for any write commands which are queued prior to said blocked high priority write command,
- selecting said write commands which are queued prior to said blocked high priority write command;
- selecting any remaining high priority commands by:
- selecting first any high priority read commands;
- selecting second any unblocked high priority write commands;
- and
- selecting normal priority commands.
A method of arbitrating between command streams, comprising:
- unblocking a blocked high priority command which is a high priority write command by
- elevating a priority level for any write commands which are queued prior to said blocked high priority write command,
- selecting said write commands which are queued prior to said blocked high priority write command;
- selecting any remaining high priority commands;
- and
- selecting normal priority commands by:
- unblocking any blocked normal priority writes;
- and
- selecting any remaining normal priority commands.
A method of ordering commands which are received from a graphics accelerator and dispatched to a memory circuit, the method comprising the steps of:
- receiving a plurality of read commands;
- selecting at least one of said plurality of read commands;
- receiving a plurality of write commands;
- receiving a blocked write command which is blocked by said plurality of write commands by:
- queuing a received write command in a queue;
- and
- testing whether said received write command is blocked when said received write command reaches a head of said queue;
- and
- unblocking, prior to completing said plurality of read commands, said blocked write command by
- elevating a priority level for any write commands which are queued prior to said blocked write command, and
- selecting said write commands which are queued prior to said blocked write command.
A method of ordering commands which are received from a graphics accelerator and dispatched to a memory circuit, the method comprising:
- receiving a plurality of read commands wherein said plurality of read commands are normal priority read commands;
- selecting at least one of said plurality of read commands;
- receiving a plurality of write commands;
- receiving a blocked write command which is blocked by said plurality of write commands wherein said blocked write command is a high priority write command and
- unblocking, prior to completing said plurality of read commands, said blocked write command by
- elevating a priority level for any write commands which are queued prior to said blocked write command, and
- selecting said write commands which are queued prior to said blocked write command.
Dependencies are inferred from the claim text.