Apparatus and method for programmable delays using a boundary-scan chain
AssigneeSun Microsystems, Inc.
InventorWillem De Lange
Life of this patent
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Abstract
The invention is a system that provides programmable clock delays for logic circuits. The system makes use of the boundary-scan register chain incorporated into logic devices for testing purposes. In the invention, delay code values are loaded through the boundary-scan register chain into delay code registers. The delay codes are then used to program the value of delay elements in the logic circuit. An evaluation logic circuit can be included to compare the output data with an expected test pattern and thereby verify the acceptability of the delay values. The invention thereby allows delays to be adjusted to correct functionality and/or optimize circuit performance without requiring modifications to the circuit design.
Claims9
A method of controlling delays in a logic circuit, said method comprising the steps of:
- loading delay codes through a boundary-scan register chain into delay code memory elements;
- and
- executing logic operations in said logic circuit having delays controlled by said delay codes of said delay code memory elements.
A programmable delay logic device, comprising:
- a logic circuit;
- a plurality of serially connected boundary-scan registers, coupled to said logic circuit, to receive delay codes;
- a delay code memory element coupled to one of said boundary-scan registers to receive a selected delay code;
- and
- a programmable delay element coupled to said delay code memory element, said programmable delay element creating a predetermined delay in response to said selected delay code.
Dependencies are inferred from the claim text.