Read/write timing for maximum utilization of bidirectional read/write bus
AssigneeAdvanced Memory International, Inc.
InventorPeter Bruce Gillingham
Life of this patent
Estimating the term…
Abstract
A method and apparatus for optimizing the efficiency of a data bus for a memory device. Extra latency is added between the time a memory controller issues a write instruction and the time the data is transferred on the data bus. This additional latency is optimized to reduce the number of idle time slots on the data bus when switching between a read instruction and a write instruction. Programmable registers are provided for adjusting the amount of latency.
Claims17
A method of transferring data on a data bus to and from a memory device, comprising the steps of:
- issuing a read instruction to the memory device;
- transferring read data from the memory device after a first time period;
- issuing a write instruction to the memory device;
- and
- delaying a transfer of write data to the memory device for a second time period, wherein the length of the second time period is within two time slots of the length of the first time period.
A memory system, comprising:
- a memory device;
- a command bus for transferring read instructions and write instructions to the memory device;
- a data bus for transferring read data from the memory device in response to read instructions, the read data being transferred on the data bus a first time period after the read instruction, and for transferring write data to the memory device in response to write instructions, the write data being transferred on the data bus a second time period after the write instruction;
- and
- a memory controller for controlling the flow of data on the data bus, wherein the length of the second time period is subject to control of a first programmable register.
A memory device, comprising:
- a data bus;
- first and second memory array banks coupled to said data bus;
- first and second delay registers, the first delay register specifying a first time period and the second delay register specifying a second time period;
- and
- a command decoder for receiving a write instruction for the first memory array bank and a read instruction for the second memory array bank, wherein data is transferred on the data bus to the first memory array bank following a delay of the first time period after the command decoder receives the write instruction, and data is transferred to the second memory array bank following a delay of the second time period after the command decoder receives the write instruction.
Dependencies are inferred from the claim text.